1//===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM VFP instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>; 15def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>, 16 SDTCisSameAs<1, 2>]>; 17 18def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>; 19def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>; 20def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>; 21def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>; 22 23//===----------------------------------------------------------------------===// 24// Operand Definitions. 25// 26 27// 8-bit floating-point immediate encodings. 28def FPImmOperand : AsmOperandClass { 29 let Name = "FPImm"; 30 let ParserMethod = "parseFPImm"; 31} 32 33def vfp_f32imm : Operand<f32>, 34 PatLeaf<(f32 fpimm), [{ 35 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1; 36 }], SDNodeXForm<fpimm, [{ 37 APFloat InVal = N->getValueAPF(); 38 uint32_t enc = ARM_AM::getFP32Imm(InVal); 39 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); 40 }]>> { 41 let PrintMethod = "printFPImmOperand"; 42 let ParserMatchClass = FPImmOperand; 43} 44 45def vfp_f64imm : Operand<f64>, 46 PatLeaf<(f64 fpimm), [{ 47 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1; 48 }], SDNodeXForm<fpimm, [{ 49 APFloat InVal = N->getValueAPF(); 50 uint32_t enc = ARM_AM::getFP64Imm(InVal); 51 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); 52 }]>> { 53 let PrintMethod = "printFPImmOperand"; 54 let ParserMatchClass = FPImmOperand; 55} 56 57def alignedload32 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 58 return cast<LoadSDNode>(N)->getAlignment() >= 4; 59}]>; 60 61def alignedstore32 : PatFrag<(ops node:$val, node:$ptr), 62 (store node:$val, node:$ptr), [{ 63 return cast<StoreSDNode>(N)->getAlignment() >= 4; 64}]>; 65 66// The VCVT to/from fixed-point instructions encode the 'fbits' operand 67// (the number of fixed bits) differently than it appears in the assembly 68// source. It's encoded as "Size - fbits" where Size is the size of the 69// fixed-point representation (32 or 16) and fbits is the value appearing 70// in the assembly source, an integer in [0,16] or (0,32], depending on size. 71def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; } 72def fbits32 : Operand<i32> { 73 let PrintMethod = "printFBits32"; 74 let ParserMatchClass = fbits32_asm_operand; 75} 76 77def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; } 78def fbits16 : Operand<i32> { 79 let PrintMethod = "printFBits16"; 80 let ParserMatchClass = fbits16_asm_operand; 81} 82 83//===----------------------------------------------------------------------===// 84// Load / store Instructions. 85// 86 87let canFoldAsLoad = 1, isReMaterializable = 1 in { 88 89def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr), 90 IIC_fpLoad64, "vldr", "\t$Dd, $addr", 91 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>; 92 93def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr), 94 IIC_fpLoad32, "vldr", "\t$Sd, $addr", 95 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]> { 96 // Some single precision VFP instructions may be executed on both NEON and VFP 97 // pipelines. 98 let D = VFPNeonDomain; 99} 100 101} // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in' 102 103def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr), 104 IIC_fpStore64, "vstr", "\t$Dd, $addr", 105 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>; 106 107def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr), 108 IIC_fpStore32, "vstr", "\t$Sd, $addr", 109 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]> { 110 // Some single precision VFP instructions may be executed on both NEON and VFP 111 // pipelines. 112 let D = VFPNeonDomain; 113} 114 115//===----------------------------------------------------------------------===// 116// Load / store multiple Instructions. 117// 118 119multiclass vfp_ldst_mult<string asm, bit L_bit, 120 InstrItinClass itin, InstrItinClass itin_upd> { 121 // Double Precision 122 def DIA : 123 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 124 IndexModeNone, itin, 125 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> { 126 let Inst{24-23} = 0b01; // Increment After 127 let Inst{21} = 0; // No writeback 128 let Inst{20} = L_bit; 129 } 130 def DIA_UPD : 131 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, 132 variable_ops), 133 IndexModeUpd, itin_upd, 134 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 135 let Inst{24-23} = 0b01; // Increment After 136 let Inst{21} = 1; // Writeback 137 let Inst{20} = L_bit; 138 } 139 def DDB_UPD : 140 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, 141 variable_ops), 142 IndexModeUpd, itin_upd, 143 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 144 let Inst{24-23} = 0b10; // Decrement Before 145 let Inst{21} = 1; // Writeback 146 let Inst{20} = L_bit; 147 } 148 149 // Single Precision 150 def SIA : 151 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops), 152 IndexModeNone, itin, 153 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> { 154 let Inst{24-23} = 0b01; // Increment After 155 let Inst{21} = 0; // No writeback 156 let Inst{20} = L_bit; 157 158 // Some single precision VFP instructions may be executed on both NEON and 159 // VFP pipelines. 160 let D = VFPNeonDomain; 161 } 162 def SIA_UPD : 163 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, 164 variable_ops), 165 IndexModeUpd, itin_upd, 166 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 167 let Inst{24-23} = 0b01; // Increment After 168 let Inst{21} = 1; // Writeback 169 let Inst{20} = L_bit; 170 171 // Some single precision VFP instructions may be executed on both NEON and 172 // VFP pipelines. 173 let D = VFPNeonDomain; 174 } 175 def SDB_UPD : 176 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, 177 variable_ops), 178 IndexModeUpd, itin_upd, 179 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 180 let Inst{24-23} = 0b10; // Decrement Before 181 let Inst{21} = 1; // Writeback 182 let Inst{20} = L_bit; 183 184 // Some single precision VFP instructions may be executed on both NEON and 185 // VFP pipelines. 186 let D = VFPNeonDomain; 187 } 188} 189 190let hasSideEffects = 0 in { 191 192let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 193defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>; 194 195let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 196defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpStore_m, IIC_fpStore_mu>; 197 198} // hasSideEffects 199 200def : MnemonicAlias<"vldm", "vldmia">; 201def : MnemonicAlias<"vstm", "vstmia">; 202 203// FLDM/FSTM - Load / Store multiple single / double precision registers for 204// pre-ARMv6 cores. 205// These instructions are deprecated! 206def : VFP2MnemonicAlias<"fldmias", "vldmia">; 207def : VFP2MnemonicAlias<"fldmdbs", "vldmdb">; 208def : VFP2MnemonicAlias<"fldmeas", "vldmdb">; 209def : VFP2MnemonicAlias<"fldmfds", "vldmia">; 210def : VFP2MnemonicAlias<"fldmiad", "vldmia">; 211def : VFP2MnemonicAlias<"fldmdbd", "vldmdb">; 212def : VFP2MnemonicAlias<"fldmead", "vldmdb">; 213def : VFP2MnemonicAlias<"fldmfdd", "vldmia">; 214 215def : VFP2MnemonicAlias<"fstmias", "vstmia">; 216def : VFP2MnemonicAlias<"fstmdbs", "vstmdb">; 217def : VFP2MnemonicAlias<"fstmeas", "vstmia">; 218def : VFP2MnemonicAlias<"fstmfds", "vstmdb">; 219def : VFP2MnemonicAlias<"fstmiad", "vstmia">; 220def : VFP2MnemonicAlias<"fstmdbd", "vstmdb">; 221def : VFP2MnemonicAlias<"fstmead", "vstmia">; 222def : VFP2MnemonicAlias<"fstmfdd", "vstmdb">; 223 224def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>, 225 Requires<[HasVFP2]>; 226def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>, 227 Requires<[HasVFP2]>; 228def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>, 229 Requires<[HasVFP2]>; 230def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>, 231 Requires<[HasVFP2]>; 232defm : VFPDTAnyInstAlias<"vpush${p}", "$r", 233 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>; 234defm : VFPDTAnyInstAlias<"vpush${p}", "$r", 235 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>; 236defm : VFPDTAnyInstAlias<"vpop${p}", "$r", 237 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>; 238defm : VFPDTAnyInstAlias<"vpop${p}", "$r", 239 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>; 240 241// FLDMX, FSTMX - Load and store multiple unknown precision registers for 242// pre-armv6 cores. 243// These instruction are deprecated so we don't want them to get selected. 244multiclass vfp_ldstx_mult<string asm, bit L_bit> { 245 // Unknown precision 246 def XIA : 247 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 248 IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> { 249 let Inst{24-23} = 0b01; // Increment After 250 let Inst{21} = 0; // No writeback 251 let Inst{20} = L_bit; 252 } 253 def XIA_UPD : 254 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 255 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 256 let Inst{24-23} = 0b01; // Increment After 257 let Inst{21} = 1; // Writeback 258 let Inst{20} = L_bit; 259 } 260 def XDB_UPD : 261 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 262 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 263 let Inst{24-23} = 0b10; // Decrement Before 264 let Inst{21} = 1; // Writeback 265 let Inst{20} = L_bit; 266 } 267} 268 269defm FLDM : vfp_ldstx_mult<"fldm", 1>; 270defm FSTM : vfp_ldstx_mult<"fstm", 0>; 271 272def : VFP2MnemonicAlias<"fldmeax", "fldmdbx">; 273def : VFP2MnemonicAlias<"fldmfdx", "fldmiax">; 274 275def : VFP2MnemonicAlias<"fstmeax", "fstmiax">; 276def : VFP2MnemonicAlias<"fstmfdx", "fstmdbx">; 277 278//===----------------------------------------------------------------------===// 279// FP Binary Operations. 280// 281 282let TwoOperandAliasConstraint = "$Dn = $Dd" in 283def VADDD : ADbI<0b11100, 0b11, 0, 0, 284 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 285 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm", 286 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>; 287 288let TwoOperandAliasConstraint = "$Sn = $Sd" in 289def VADDS : ASbIn<0b11100, 0b11, 0, 0, 290 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 291 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm", 292 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> { 293 // Some single precision VFP instructions may be executed on both NEON and 294 // VFP pipelines on A8. 295 let D = VFPNeonA8Domain; 296} 297 298let TwoOperandAliasConstraint = "$Dn = $Dd" in 299def VSUBD : ADbI<0b11100, 0b11, 1, 0, 300 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 301 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm", 302 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>; 303 304let TwoOperandAliasConstraint = "$Sn = $Sd" in 305def VSUBS : ASbIn<0b11100, 0b11, 1, 0, 306 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 307 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm", 308 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> { 309 // Some single precision VFP instructions may be executed on both NEON and 310 // VFP pipelines on A8. 311 let D = VFPNeonA8Domain; 312} 313 314let TwoOperandAliasConstraint = "$Dn = $Dd" in 315def VDIVD : ADbI<0b11101, 0b00, 0, 0, 316 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 317 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm", 318 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>; 319 320let TwoOperandAliasConstraint = "$Sn = $Sd" in 321def VDIVS : ASbI<0b11101, 0b00, 0, 0, 322 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 323 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm", 324 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>; 325 326let TwoOperandAliasConstraint = "$Dn = $Dd" in 327def VMULD : ADbI<0b11100, 0b10, 0, 0, 328 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 329 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm", 330 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>; 331 332let TwoOperandAliasConstraint = "$Sn = $Sd" in 333def VMULS : ASbIn<0b11100, 0b10, 0, 0, 334 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 335 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm", 336 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> { 337 // Some single precision VFP instructions may be executed on both NEON and 338 // VFP pipelines on A8. 339 let D = VFPNeonA8Domain; 340} 341 342def VNMULD : ADbI<0b11100, 0b10, 1, 0, 343 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 344 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm", 345 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>; 346 347def VNMULS : ASbI<0b11100, 0b10, 1, 0, 348 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 349 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm", 350 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> { 351 // Some single precision VFP instructions may be executed on both NEON and 352 // VFP pipelines on A8. 353 let D = VFPNeonA8Domain; 354} 355 356multiclass vsel_inst<string op, bits<2> opc, int CC> { 357 let DecoderNamespace = "VFPV8", PostEncoderMethod = "", 358 Uses = [CPSR], AddedComplexity = 4 in { 359 def S : ASbInp<0b11100, opc, 0, 360 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 361 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"), 362 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>, 363 Requires<[HasFPARMv8]>; 364 365 def D : ADbInp<0b11100, opc, 0, 366 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 367 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"), 368 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>, 369 Requires<[HasFPARMv8, HasDPVFP]>; 370 } 371} 372 373// The CC constants here match ARMCC::CondCodes. 374defm VSELGT : vsel_inst<"gt", 0b11, 12>; 375defm VSELGE : vsel_inst<"ge", 0b10, 10>; 376defm VSELEQ : vsel_inst<"eq", 0b00, 0>; 377defm VSELVS : vsel_inst<"vs", 0b01, 6>; 378 379multiclass vmaxmin_inst<string op, bit opc, SDNode SD> { 380 let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in { 381 def S : ASbInp<0b11101, 0b00, opc, 382 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 383 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"), 384 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>, 385 Requires<[HasFPARMv8]>; 386 387 def D : ADbInp<0b11101, 0b00, opc, 388 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 389 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"), 390 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>, 391 Requires<[HasFPARMv8, HasDPVFP]>; 392 } 393} 394 395defm VMAXNM : vmaxmin_inst<"vmaxnm", 0, fmaxnum>; 396defm VMINNM : vmaxmin_inst<"vminnm", 1, fminnum>; 397 398// Match reassociated forms only if not sign dependent rounding. 399def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)), 400 (VNMULD DPR:$a, DPR:$b)>, 401 Requires<[NoHonorSignDependentRounding,HasDPVFP]>; 402def : Pat<(fmul (fneg SPR:$a), SPR:$b), 403 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>; 404 405// These are encoded as unary instructions. 406let Defs = [FPSCR_NZCV] in { 407def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0, 408 (outs), (ins DPR:$Dd, DPR:$Dm), 409 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm", 410 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>; 411 412def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0, 413 (outs), (ins SPR:$Sd, SPR:$Sm), 414 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm", 415 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> { 416 // Some single precision VFP instructions may be executed on both NEON and 417 // VFP pipelines on A8. 418 let D = VFPNeonA8Domain; 419} 420 421// FIXME: Verify encoding after integrated assembler is working. 422def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0, 423 (outs), (ins DPR:$Dd, DPR:$Dm), 424 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm", 425 [/* For disassembly only; pattern left blank */]>; 426 427def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0, 428 (outs), (ins SPR:$Sd, SPR:$Sm), 429 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm", 430 [/* For disassembly only; pattern left blank */]> { 431 // Some single precision VFP instructions may be executed on both NEON and 432 // VFP pipelines on A8. 433 let D = VFPNeonA8Domain; 434} 435} // Defs = [FPSCR_NZCV] 436 437//===----------------------------------------------------------------------===// 438// FP Unary Operations. 439// 440 441def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0, 442 (outs DPR:$Dd), (ins DPR:$Dm), 443 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm", 444 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>; 445 446def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0, 447 (outs SPR:$Sd), (ins SPR:$Sm), 448 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm", 449 [(set SPR:$Sd, (fabs SPR:$Sm))]> { 450 // Some single precision VFP instructions may be executed on both NEON and 451 // VFP pipelines on A8. 452 let D = VFPNeonA8Domain; 453} 454 455let Defs = [FPSCR_NZCV] in { 456def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0, 457 (outs), (ins DPR:$Dd), 458 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0", 459 [(arm_cmpfp0 (f64 DPR:$Dd))]> { 460 let Inst{3-0} = 0b0000; 461 let Inst{5} = 0; 462} 463 464def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0, 465 (outs), (ins SPR:$Sd), 466 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0", 467 [(arm_cmpfp0 SPR:$Sd)]> { 468 let Inst{3-0} = 0b0000; 469 let Inst{5} = 0; 470 471 // Some single precision VFP instructions may be executed on both NEON and 472 // VFP pipelines on A8. 473 let D = VFPNeonA8Domain; 474} 475 476// FIXME: Verify encoding after integrated assembler is working. 477def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0, 478 (outs), (ins DPR:$Dd), 479 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0", 480 [/* For disassembly only; pattern left blank */]> { 481 let Inst{3-0} = 0b0000; 482 let Inst{5} = 0; 483} 484 485def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0, 486 (outs), (ins SPR:$Sd), 487 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0", 488 [/* For disassembly only; pattern left blank */]> { 489 let Inst{3-0} = 0b0000; 490 let Inst{5} = 0; 491 492 // Some single precision VFP instructions may be executed on both NEON and 493 // VFP pipelines on A8. 494 let D = VFPNeonA8Domain; 495} 496} // Defs = [FPSCR_NZCV] 497 498def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0, 499 (outs DPR:$Dd), (ins SPR:$Sm), 500 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm", 501 [(set DPR:$Dd, (fextend SPR:$Sm))]> { 502 // Instruction operands. 503 bits<5> Dd; 504 bits<5> Sm; 505 506 // Encode instruction operands. 507 let Inst{3-0} = Sm{4-1}; 508 let Inst{5} = Sm{0}; 509 let Inst{15-12} = Dd{3-0}; 510 let Inst{22} = Dd{4}; 511 512 let Predicates = [HasVFP2, HasDPVFP]; 513} 514 515// Special case encoding: bits 11-8 is 0b1011. 516def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm, 517 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm", 518 [(set SPR:$Sd, (fround DPR:$Dm))]> { 519 // Instruction operands. 520 bits<5> Sd; 521 bits<5> Dm; 522 523 // Encode instruction operands. 524 let Inst{3-0} = Dm{3-0}; 525 let Inst{5} = Dm{4}; 526 let Inst{15-12} = Sd{4-1}; 527 let Inst{22} = Sd{0}; 528 529 let Inst{27-23} = 0b11101; 530 let Inst{21-16} = 0b110111; 531 let Inst{11-8} = 0b1011; 532 let Inst{7-6} = 0b11; 533 let Inst{4} = 0; 534 535 let Predicates = [HasVFP2, HasDPVFP]; 536} 537 538// Between half, single and double-precision. For disassembly only. 539 540// FIXME: Verify encoding after integrated assembler is working. 541def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), 542 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm", 543 [/* For disassembly only; pattern left blank */]>, 544 Requires<[HasFP16]>; 545 546def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), 547 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm", 548 [/* For disassembly only; pattern left blank */]>, 549 Requires<[HasFP16]>; 550 551def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), 552 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm", 553 [/* For disassembly only; pattern left blank */]>, 554 Requires<[HasFP16]>; 555 556def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), 557 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm", 558 [/* For disassembly only; pattern left blank */]>, 559 Requires<[HasFP16]>; 560 561def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0, 562 (outs DPR:$Dd), (ins SPR:$Sm), 563 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm", 564 []>, Requires<[HasFPARMv8, HasDPVFP]> { 565 // Instruction operands. 566 bits<5> Sm; 567 568 // Encode instruction operands. 569 let Inst{3-0} = Sm{4-1}; 570 let Inst{5} = Sm{0}; 571} 572 573def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0, 574 (outs SPR:$Sd), (ins DPR:$Dm), 575 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm", 576 []>, Requires<[HasFPARMv8, HasDPVFP]> { 577 // Instruction operands. 578 bits<5> Sd; 579 bits<5> Dm; 580 581 // Encode instruction operands. 582 let Inst{3-0} = Dm{3-0}; 583 let Inst{5} = Dm{4}; 584 let Inst{15-12} = Sd{4-1}; 585 let Inst{22} = Sd{0}; 586} 587 588def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0, 589 (outs DPR:$Dd), (ins SPR:$Sm), 590 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm", 591 []>, Requires<[HasFPARMv8, HasDPVFP]> { 592 // Instruction operands. 593 bits<5> Sm; 594 595 // Encode instruction operands. 596 let Inst{3-0} = Sm{4-1}; 597 let Inst{5} = Sm{0}; 598} 599 600def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0, 601 (outs SPR:$Sd), (ins DPR:$Dm), 602 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm", 603 []>, Requires<[HasFPARMv8, HasDPVFP]> { 604 // Instruction operands. 605 bits<5> Sd; 606 bits<5> Dm; 607 608 // Encode instruction operands. 609 let Inst{15-12} = Sd{4-1}; 610 let Inst{22} = Sd{0}; 611 let Inst{3-0} = Dm{3-0}; 612 let Inst{5} = Dm{4}; 613} 614 615def : Pat<(fp_to_f16 SPR:$a), 616 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>; 617 618def : Pat<(fp_to_f16 (f64 DPR:$a)), 619 (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>; 620 621def : Pat<(f16_to_fp GPR:$a), 622 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>; 623 624def : Pat<(f64 (f16_to_fp GPR:$a)), 625 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>; 626 627multiclass vcvt_inst<string opc, bits<2> rm, 628 SDPatternOperator node = null_frag> { 629 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in { 630 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0, 631 (outs SPR:$Sd), (ins SPR:$Sm), 632 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"), 633 []>, 634 Requires<[HasFPARMv8]> { 635 let Inst{17-16} = rm; 636 } 637 638 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0, 639 (outs SPR:$Sd), (ins SPR:$Sm), 640 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"), 641 []>, 642 Requires<[HasFPARMv8]> { 643 let Inst{17-16} = rm; 644 } 645 646 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0, 647 (outs SPR:$Sd), (ins DPR:$Dm), 648 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"), 649 []>, 650 Requires<[HasFPARMv8, HasDPVFP]> { 651 bits<5> Dm; 652 653 let Inst{17-16} = rm; 654 655 // Encode instruction operands 656 let Inst{3-0} = Dm{3-0}; 657 let Inst{5} = Dm{4}; 658 let Inst{8} = 1; 659 } 660 661 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0, 662 (outs SPR:$Sd), (ins DPR:$Dm), 663 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"), 664 []>, 665 Requires<[HasFPARMv8, HasDPVFP]> { 666 bits<5> Dm; 667 668 let Inst{17-16} = rm; 669 670 // Encode instruction operands 671 let Inst{3-0} = Dm{3-0}; 672 let Inst{5} = Dm{4}; 673 let Inst{8} = 1; 674 } 675 } 676 677 let Predicates = [HasFPARMv8] in { 678 def : Pat<(i32 (fp_to_sint (node SPR:$a))), 679 (COPY_TO_REGCLASS 680 (!cast<Instruction>(NAME#"SS") SPR:$a), 681 GPR)>; 682 def : Pat<(i32 (fp_to_uint (node SPR:$a))), 683 (COPY_TO_REGCLASS 684 (!cast<Instruction>(NAME#"US") SPR:$a), 685 GPR)>; 686 } 687 let Predicates = [HasFPARMv8, HasDPVFP] in { 688 def : Pat<(i32 (fp_to_sint (node (f64 DPR:$a)))), 689 (COPY_TO_REGCLASS 690 (!cast<Instruction>(NAME#"SD") DPR:$a), 691 GPR)>; 692 def : Pat<(i32 (fp_to_uint (node (f64 DPR:$a)))), 693 (COPY_TO_REGCLASS 694 (!cast<Instruction>(NAME#"UD") DPR:$a), 695 GPR)>; 696 } 697} 698 699defm VCVTA : vcvt_inst<"a", 0b00, frnd>; 700defm VCVTN : vcvt_inst<"n", 0b01>; 701defm VCVTP : vcvt_inst<"p", 0b10, fceil>; 702defm VCVTM : vcvt_inst<"m", 0b11, ffloor>; 703 704def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, 705 (outs DPR:$Dd), (ins DPR:$Dm), 706 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm", 707 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>; 708 709def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0, 710 (outs SPR:$Sd), (ins SPR:$Sm), 711 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm", 712 [(set SPR:$Sd, (fneg SPR:$Sm))]> { 713 // Some single precision VFP instructions may be executed on both NEON and 714 // VFP pipelines on A8. 715 let D = VFPNeonA8Domain; 716} 717 718multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> { 719 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0, 720 (outs SPR:$Sd), (ins SPR:$Sm), 721 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm", 722 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>, 723 Requires<[HasFPARMv8]> { 724 let Inst{7} = op2; 725 let Inst{16} = op; 726 } 727 def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0, 728 (outs DPR:$Dd), (ins DPR:$Dm), 729 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm", 730 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>, 731 Requires<[HasFPARMv8, HasDPVFP]> { 732 let Inst{7} = op2; 733 let Inst{16} = op; 734 } 735 736 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"), 737 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>, 738 Requires<[HasFPARMv8]>; 739 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"), 740 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p)>, 741 Requires<[HasFPARMv8,HasDPVFP]>; 742} 743 744defm VRINTZ : vrint_inst_zrx<"z", 0, 1, ftrunc>; 745defm VRINTR : vrint_inst_zrx<"r", 0, 0, fnearbyint>; 746defm VRINTX : vrint_inst_zrx<"x", 1, 0, frint>; 747 748multiclass vrint_inst_anpm<string opc, bits<2> rm, 749 SDPatternOperator node = null_frag> { 750 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in { 751 def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0, 752 (outs SPR:$Sd), (ins SPR:$Sm), 753 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"), 754 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>, 755 Requires<[HasFPARMv8]> { 756 let Inst{17-16} = rm; 757 } 758 def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0, 759 (outs DPR:$Dd), (ins DPR:$Dm), 760 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"), 761 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>, 762 Requires<[HasFPARMv8, HasDPVFP]> { 763 let Inst{17-16} = rm; 764 } 765 } 766 767 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"), 768 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm)>, 769 Requires<[HasFPARMv8]>; 770 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"), 771 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>, 772 Requires<[HasFPARMv8,HasDPVFP]>; 773} 774 775defm VRINTA : vrint_inst_anpm<"a", 0b00, frnd>; 776defm VRINTN : vrint_inst_anpm<"n", 0b01>; 777defm VRINTP : vrint_inst_anpm<"p", 0b10, fceil>; 778defm VRINTM : vrint_inst_anpm<"m", 0b11, ffloor>; 779 780def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0, 781 (outs DPR:$Dd), (ins DPR:$Dm), 782 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm", 783 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>; 784 785def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0, 786 (outs SPR:$Sd), (ins SPR:$Sm), 787 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm", 788 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>; 789 790let hasSideEffects = 0 in { 791def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0, 792 (outs DPR:$Dd), (ins DPR:$Dm), 793 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>; 794 795def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0, 796 (outs SPR:$Sd), (ins SPR:$Sm), 797 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>; 798} // hasSideEffects 799 800//===----------------------------------------------------------------------===// 801// FP <-> GPR Copies. Int <-> FP Conversions. 802// 803 804def VMOVRS : AVConv2I<0b11100001, 0b1010, 805 (outs GPR:$Rt), (ins SPR:$Sn), 806 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn", 807 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> { 808 // Instruction operands. 809 bits<4> Rt; 810 bits<5> Sn; 811 812 // Encode instruction operands. 813 let Inst{19-16} = Sn{4-1}; 814 let Inst{7} = Sn{0}; 815 let Inst{15-12} = Rt; 816 817 let Inst{6-5} = 0b00; 818 let Inst{3-0} = 0b0000; 819 820 // Some single precision VFP instructions may be executed on both NEON and VFP 821 // pipelines. 822 let D = VFPNeonDomain; 823} 824 825// Bitcast i32 -> f32. NEON prefers to use VMOVDRR. 826def VMOVSR : AVConv4I<0b11100000, 0b1010, 827 (outs SPR:$Sn), (ins GPR:$Rt), 828 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt", 829 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>, 830 Requires<[HasVFP2, UseVMOVSR]> { 831 // Instruction operands. 832 bits<5> Sn; 833 bits<4> Rt; 834 835 // Encode instruction operands. 836 let Inst{19-16} = Sn{4-1}; 837 let Inst{7} = Sn{0}; 838 let Inst{15-12} = Rt; 839 840 let Inst{6-5} = 0b00; 841 let Inst{3-0} = 0b0000; 842 843 // Some single precision VFP instructions may be executed on both NEON and VFP 844 // pipelines. 845 let D = VFPNeonDomain; 846} 847 848let hasSideEffects = 0 in { 849def VMOVRRD : AVConv3I<0b11000101, 0b1011, 850 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm), 851 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm", 852 [/* FIXME: Can't write pattern for multiple result instr*/]> { 853 // Instruction operands. 854 bits<5> Dm; 855 bits<4> Rt; 856 bits<4> Rt2; 857 858 // Encode instruction operands. 859 let Inst{3-0} = Dm{3-0}; 860 let Inst{5} = Dm{4}; 861 let Inst{15-12} = Rt; 862 let Inst{19-16} = Rt2; 863 864 let Inst{7-6} = 0b00; 865 866 // Some single precision VFP instructions may be executed on both NEON and VFP 867 // pipelines. 868 let D = VFPNeonDomain; 869 870 // This instruction is equivalent to 871 // $Rt = EXTRACT_SUBREG $Dm, ssub_0 872 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1 873 let isExtractSubreg = 1; 874} 875 876def VMOVRRS : AVConv3I<0b11000101, 0b1010, 877 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2), 878 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2", 879 [/* For disassembly only; pattern left blank */]> { 880 bits<5> src1; 881 bits<4> Rt; 882 bits<4> Rt2; 883 884 // Encode instruction operands. 885 let Inst{3-0} = src1{4-1}; 886 let Inst{5} = src1{0}; 887 let Inst{15-12} = Rt; 888 let Inst{19-16} = Rt2; 889 890 let Inst{7-6} = 0b00; 891 892 // Some single precision VFP instructions may be executed on both NEON and VFP 893 // pipelines. 894 let D = VFPNeonDomain; 895 let DecoderMethod = "DecodeVMOVRRS"; 896} 897} // hasSideEffects 898 899// FMDHR: GPR -> SPR 900// FMDLR: GPR -> SPR 901 902def VMOVDRR : AVConv5I<0b11000100, 0b1011, 903 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2), 904 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2", 905 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> { 906 // Instruction operands. 907 bits<5> Dm; 908 bits<4> Rt; 909 bits<4> Rt2; 910 911 // Encode instruction operands. 912 let Inst{3-0} = Dm{3-0}; 913 let Inst{5} = Dm{4}; 914 let Inst{15-12} = Rt; 915 let Inst{19-16} = Rt2; 916 917 let Inst{7-6} = 0b00; 918 919 // Some single precision VFP instructions may be executed on both NEON and VFP 920 // pipelines. 921 let D = VFPNeonDomain; 922 923 // This instruction is equivalent to 924 // $Dm = REG_SEQUENCE $Rt, ssub_0, $Rt2, ssub_1 925 let isRegSequence = 1; 926} 927 928// Hoist an fabs or a fneg of a value coming from integer registers 929// and do the fabs/fneg on the integer value. This is never a lose 930// and could enable the conversion to float to be removed completely. 931def : Pat<(fabs (arm_fmdrr GPR:$Rl, GPR:$Rh)), 932 (VMOVDRR GPR:$Rl, (BFC GPR:$Rh, (i32 0x7FFFFFFF)))>, 933 Requires<[IsARM]>; 934def : Pat<(fabs (arm_fmdrr GPR:$Rl, GPR:$Rh)), 935 (VMOVDRR GPR:$Rl, (t2BFC GPR:$Rh, (i32 0x7FFFFFFF)))>, 936 Requires<[IsThumb2]>; 937def : Pat<(fneg (arm_fmdrr GPR:$Rl, GPR:$Rh)), 938 (VMOVDRR GPR:$Rl, (EORri GPR:$Rh, (i32 0x80000000)))>, 939 Requires<[IsARM]>; 940def : Pat<(fneg (arm_fmdrr GPR:$Rl, GPR:$Rh)), 941 (VMOVDRR GPR:$Rl, (t2EORri GPR:$Rh, (i32 0x80000000)))>, 942 Requires<[IsThumb2]>; 943 944let hasSideEffects = 0 in 945def VMOVSRR : AVConv5I<0b11000100, 0b1010, 946 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2), 947 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2", 948 [/* For disassembly only; pattern left blank */]> { 949 // Instruction operands. 950 bits<5> dst1; 951 bits<4> src1; 952 bits<4> src2; 953 954 // Encode instruction operands. 955 let Inst{3-0} = dst1{4-1}; 956 let Inst{5} = dst1{0}; 957 let Inst{15-12} = src1; 958 let Inst{19-16} = src2; 959 960 let Inst{7-6} = 0b00; 961 962 // Some single precision VFP instructions may be executed on both NEON and VFP 963 // pipelines. 964 let D = VFPNeonDomain; 965 966 let DecoderMethod = "DecodeVMOVSRR"; 967} 968 969// FMRDH: SPR -> GPR 970// FMRDL: SPR -> GPR 971// FMRRS: SPR -> GPR 972// FMRX: SPR system reg -> GPR 973// FMSRR: GPR -> SPR 974// FMXR: GPR -> VFP system reg 975 976 977// Int -> FP: 978 979class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 980 bits<4> opcod4, dag oops, dag iops, 981 InstrItinClass itin, string opc, string asm, 982 list<dag> pattern> 983 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 984 pattern> { 985 // Instruction operands. 986 bits<5> Dd; 987 bits<5> Sm; 988 989 // Encode instruction operands. 990 let Inst{3-0} = Sm{4-1}; 991 let Inst{5} = Sm{0}; 992 let Inst{15-12} = Dd{3-0}; 993 let Inst{22} = Dd{4}; 994 995 let Predicates = [HasVFP2, HasDPVFP]; 996} 997 998class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 999 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin, 1000 string opc, string asm, list<dag> pattern> 1001 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1002 pattern> { 1003 // Instruction operands. 1004 bits<5> Sd; 1005 bits<5> Sm; 1006 1007 // Encode instruction operands. 1008 let Inst{3-0} = Sm{4-1}; 1009 let Inst{5} = Sm{0}; 1010 let Inst{15-12} = Sd{4-1}; 1011 let Inst{22} = Sd{0}; 1012} 1013 1014def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, 1015 (outs DPR:$Dd), (ins SPR:$Sm), 1016 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm", 1017 []> { 1018 let Inst{7} = 1; // s32 1019} 1020 1021let Predicates=[HasVFP2, HasDPVFP] in { 1022 def : VFPPat<(f64 (sint_to_fp GPR:$a)), 1023 (VSITOD (COPY_TO_REGCLASS GPR:$a, SPR))>; 1024 1025 def : VFPPat<(f64 (sint_to_fp (i32 (alignedload32 addrmode5:$a)))), 1026 (VSITOD (VLDRS addrmode5:$a))>; 1027} 1028 1029def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, 1030 (outs SPR:$Sd),(ins SPR:$Sm), 1031 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm", 1032 []> { 1033 let Inst{7} = 1; // s32 1034 1035 // Some single precision VFP instructions may be executed on both NEON and 1036 // VFP pipelines on A8. 1037 let D = VFPNeonA8Domain; 1038} 1039 1040def : VFPNoNEONPat<(f32 (sint_to_fp GPR:$a)), 1041 (VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))>; 1042 1043def : VFPNoNEONPat<(f32 (sint_to_fp (i32 (alignedload32 addrmode5:$a)))), 1044 (VSITOS (VLDRS addrmode5:$a))>; 1045 1046def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, 1047 (outs DPR:$Dd), (ins SPR:$Sm), 1048 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm", 1049 []> { 1050 let Inst{7} = 0; // u32 1051} 1052 1053let Predicates=[HasVFP2, HasDPVFP] in { 1054 def : VFPPat<(f64 (uint_to_fp GPR:$a)), 1055 (VUITOD (COPY_TO_REGCLASS GPR:$a, SPR))>; 1056 1057 def : VFPPat<(f64 (uint_to_fp (i32 (alignedload32 addrmode5:$a)))), 1058 (VUITOD (VLDRS addrmode5:$a))>; 1059} 1060 1061def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, 1062 (outs SPR:$Sd), (ins SPR:$Sm), 1063 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm", 1064 []> { 1065 let Inst{7} = 0; // u32 1066 1067 // Some single precision VFP instructions may be executed on both NEON and 1068 // VFP pipelines on A8. 1069 let D = VFPNeonA8Domain; 1070} 1071 1072def : VFPNoNEONPat<(f32 (uint_to_fp GPR:$a)), 1073 (VUITOS (COPY_TO_REGCLASS GPR:$a, SPR))>; 1074 1075def : VFPNoNEONPat<(f32 (uint_to_fp (i32 (alignedload32 addrmode5:$a)))), 1076 (VUITOS (VLDRS addrmode5:$a))>; 1077 1078// FP -> Int: 1079 1080class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1081 bits<4> opcod4, dag oops, dag iops, 1082 InstrItinClass itin, string opc, string asm, 1083 list<dag> pattern> 1084 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1085 pattern> { 1086 // Instruction operands. 1087 bits<5> Sd; 1088 bits<5> Dm; 1089 1090 // Encode instruction operands. 1091 let Inst{3-0} = Dm{3-0}; 1092 let Inst{5} = Dm{4}; 1093 let Inst{15-12} = Sd{4-1}; 1094 let Inst{22} = Sd{0}; 1095 1096 let Predicates = [HasVFP2, HasDPVFP]; 1097} 1098 1099class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1100 bits<4> opcod4, dag oops, dag iops, 1101 InstrItinClass itin, string opc, string asm, 1102 list<dag> pattern> 1103 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1104 pattern> { 1105 // Instruction operands. 1106 bits<5> Sd; 1107 bits<5> Sm; 1108 1109 // Encode instruction operands. 1110 let Inst{3-0} = Sm{4-1}; 1111 let Inst{5} = Sm{0}; 1112 let Inst{15-12} = Sd{4-1}; 1113 let Inst{22} = Sd{0}; 1114} 1115 1116// Always set Z bit in the instruction, i.e. "round towards zero" variants. 1117def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, 1118 (outs SPR:$Sd), (ins DPR:$Dm), 1119 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm", 1120 []> { 1121 let Inst{7} = 1; // Z bit 1122} 1123 1124let Predicates=[HasVFP2, HasDPVFP] in { 1125 def : VFPPat<(i32 (fp_to_sint (f64 DPR:$a))), 1126 (COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)>; 1127 1128 def : VFPPat<(alignedstore32 (i32 (fp_to_sint (f64 DPR:$a))), addrmode5:$ptr), 1129 (VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)>; 1130} 1131 1132def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, 1133 (outs SPR:$Sd), (ins SPR:$Sm), 1134 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm", 1135 []> { 1136 let Inst{7} = 1; // Z bit 1137 1138 // Some single precision VFP instructions may be executed on both NEON and 1139 // VFP pipelines on A8. 1140 let D = VFPNeonA8Domain; 1141} 1142 1143def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)), 1144 (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>; 1145 1146def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_sint (f32 SPR:$a))), 1147 addrmode5:$ptr), 1148 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>; 1149 1150def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, 1151 (outs SPR:$Sd), (ins DPR:$Dm), 1152 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm", 1153 []> { 1154 let Inst{7} = 1; // Z bit 1155} 1156 1157let Predicates=[HasVFP2, HasDPVFP] in { 1158 def : VFPPat<(i32 (fp_to_uint (f64 DPR:$a))), 1159 (COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)>; 1160 1161 def : VFPPat<(alignedstore32 (i32 (fp_to_uint (f64 DPR:$a))), addrmode5:$ptr), 1162 (VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)>; 1163} 1164 1165def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, 1166 (outs SPR:$Sd), (ins SPR:$Sm), 1167 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm", 1168 []> { 1169 let Inst{7} = 1; // Z bit 1170 1171 // Some single precision VFP instructions may be executed on both NEON and 1172 // VFP pipelines on A8. 1173 let D = VFPNeonA8Domain; 1174} 1175 1176def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)), 1177 (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>; 1178 1179def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_uint (f32 SPR:$a))), 1180 addrmode5:$ptr), 1181 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>; 1182 1183// And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR. 1184let Uses = [FPSCR] in { 1185// FIXME: Verify encoding after integrated assembler is working. 1186def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, 1187 (outs SPR:$Sd), (ins DPR:$Dm), 1188 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm", 1189 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{ 1190 let Inst{7} = 0; // Z bit 1191} 1192 1193def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, 1194 (outs SPR:$Sd), (ins SPR:$Sm), 1195 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm", 1196 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> { 1197 let Inst{7} = 0; // Z bit 1198} 1199 1200def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, 1201 (outs SPR:$Sd), (ins DPR:$Dm), 1202 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm", 1203 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{ 1204 let Inst{7} = 0; // Z bit 1205} 1206 1207def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, 1208 (outs SPR:$Sd), (ins SPR:$Sm), 1209 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm", 1210 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> { 1211 let Inst{7} = 0; // Z bit 1212} 1213} 1214 1215// Convert between floating-point and fixed-point 1216// Data type for fixed-point naming convention: 1217// S16 (U=0, sx=0) -> SH 1218// U16 (U=1, sx=0) -> UH 1219// S32 (U=0, sx=1) -> SL 1220// U32 (U=1, sx=1) -> UL 1221 1222let Constraints = "$a = $dst" in { 1223 1224// FP to Fixed-Point: 1225 1226// Single Precision register 1227class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, 1228 bit op5, dag oops, dag iops, InstrItinClass itin, 1229 string opc, string asm, list<dag> pattern> 1230 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>, 1231 Sched<[WriteCvtFP]> { 1232 bits<5> dst; 1233 // if dp_operation then UInt(D:Vd) else UInt(Vd:D); 1234 let Inst{22} = dst{0}; 1235 let Inst{15-12} = dst{4-1}; 1236} 1237 1238// Double Precision register 1239class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, 1240 bit op5, dag oops, dag iops, InstrItinClass itin, 1241 string opc, string asm, list<dag> pattern> 1242 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>, 1243 Sched<[WriteCvtFP]> { 1244 bits<5> dst; 1245 // if dp_operation then UInt(D:Vd) else UInt(Vd:D); 1246 let Inst{22} = dst{4}; 1247 let Inst{15-12} = dst{3-0}; 1248 1249 let Predicates = [HasVFP2, HasDPVFP]; 1250} 1251 1252def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0, 1253 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1254 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []> { 1255 // Some single precision VFP instructions may be executed on both NEON and 1256 // VFP pipelines on A8. 1257 let D = VFPNeonA8Domain; 1258} 1259 1260def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0, 1261 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1262 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []> { 1263 // Some single precision VFP instructions may be executed on both NEON and 1264 // VFP pipelines on A8. 1265 let D = VFPNeonA8Domain; 1266} 1267 1268def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1, 1269 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1270 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []> { 1271 // Some single precision VFP instructions may be executed on both NEON and 1272 // VFP pipelines on A8. 1273 let D = VFPNeonA8Domain; 1274} 1275 1276def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1, 1277 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1278 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []> { 1279 // Some single precision VFP instructions may be executed on both NEON and 1280 // VFP pipelines on A8. 1281 let D = VFPNeonA8Domain; 1282} 1283 1284def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0, 1285 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1286 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>; 1287 1288def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0, 1289 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1290 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>; 1291 1292def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1, 1293 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1294 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>; 1295 1296def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1, 1297 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1298 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>; 1299 1300// Fixed-Point to FP: 1301 1302def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0, 1303 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1304 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []> { 1305 // Some single precision VFP instructions may be executed on both NEON and 1306 // VFP pipelines on A8. 1307 let D = VFPNeonA8Domain; 1308} 1309 1310def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0, 1311 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1312 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []> { 1313 // Some single precision VFP instructions may be executed on both NEON and 1314 // VFP pipelines on A8. 1315 let D = VFPNeonA8Domain; 1316} 1317 1318def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1, 1319 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1320 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []> { 1321 // Some single precision VFP instructions may be executed on both NEON and 1322 // VFP pipelines on A8. 1323 let D = VFPNeonA8Domain; 1324} 1325 1326def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1, 1327 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1328 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []> { 1329 // Some single precision VFP instructions may be executed on both NEON and 1330 // VFP pipelines on A8. 1331 let D = VFPNeonA8Domain; 1332} 1333 1334def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0, 1335 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1336 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>; 1337 1338def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0, 1339 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1340 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>; 1341 1342def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1, 1343 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1344 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>; 1345 1346def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1, 1347 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1348 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>; 1349 1350} // End of 'let Constraints = "$a = $dst" in' 1351 1352//===----------------------------------------------------------------------===// 1353// FP Multiply-Accumulate Operations. 1354// 1355 1356def VMLAD : ADbI<0b11100, 0b00, 0, 0, 1357 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1358 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm", 1359 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm), 1360 (f64 DPR:$Ddin)))]>, 1361 RegConstraint<"$Ddin = $Dd">, 1362 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1363 1364def VMLAS : ASbIn<0b11100, 0b00, 0, 0, 1365 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1366 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm", 1367 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm), 1368 SPR:$Sdin))]>, 1369 RegConstraint<"$Sdin = $Sd">, 1370 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> { 1371 // Some single precision VFP instructions may be executed on both NEON and 1372 // VFP pipelines on A8. 1373 let D = VFPNeonA8Domain; 1374} 1375 1376def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 1377 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>, 1378 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1379def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 1380 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 1381 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx,DontUseFusedMAC]>; 1382 1383def VMLSD : ADbI<0b11100, 0b00, 1, 0, 1384 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1385 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm", 1386 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 1387 (f64 DPR:$Ddin)))]>, 1388 RegConstraint<"$Ddin = $Dd">, 1389 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1390 1391def VMLSS : ASbIn<0b11100, 0b00, 1, 0, 1392 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1393 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm", 1394 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 1395 SPR:$Sdin))]>, 1396 RegConstraint<"$Sdin = $Sd">, 1397 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> { 1398 // Some single precision VFP instructions may be executed on both NEON and 1399 // VFP pipelines on A8. 1400 let D = VFPNeonA8Domain; 1401} 1402 1403def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 1404 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, 1405 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1406def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 1407 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, 1408 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>; 1409 1410def VNMLAD : ADbI<0b11100, 0b01, 1, 0, 1411 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1412 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm", 1413 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 1414 (f64 DPR:$Ddin)))]>, 1415 RegConstraint<"$Ddin = $Dd">, 1416 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1417 1418def VNMLAS : ASbI<0b11100, 0b01, 1, 0, 1419 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1420 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm", 1421 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 1422 SPR:$Sdin))]>, 1423 RegConstraint<"$Sdin = $Sd">, 1424 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> { 1425 // Some single precision VFP instructions may be executed on both NEON and 1426 // VFP pipelines on A8. 1427 let D = VFPNeonA8Domain; 1428} 1429 1430def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin), 1431 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, 1432 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1433def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin), 1434 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 1435 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>; 1436 1437def VNMLSD : ADbI<0b11100, 0b01, 0, 0, 1438 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1439 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm", 1440 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm), 1441 (f64 DPR:$Ddin)))]>, 1442 RegConstraint<"$Ddin = $Dd">, 1443 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1444 1445def VNMLSS : ASbI<0b11100, 0b01, 0, 0, 1446 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1447 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm", 1448 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, 1449 RegConstraint<"$Sdin = $Sd">, 1450 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> { 1451 // Some single precision VFP instructions may be executed on both NEON and 1452 // VFP pipelines on A8. 1453 let D = VFPNeonA8Domain; 1454} 1455 1456def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin), 1457 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>, 1458 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1459def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin), 1460 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>, 1461 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>; 1462 1463//===----------------------------------------------------------------------===// 1464// Fused FP Multiply-Accumulate Operations. 1465// 1466def VFMAD : ADbI<0b11101, 0b10, 0, 0, 1467 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1468 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm", 1469 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm), 1470 (f64 DPR:$Ddin)))]>, 1471 RegConstraint<"$Ddin = $Dd">, 1472 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1473 1474def VFMAS : ASbIn<0b11101, 0b10, 0, 0, 1475 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1476 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm", 1477 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm), 1478 SPR:$Sdin))]>, 1479 RegConstraint<"$Sdin = $Sd">, 1480 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> { 1481 // Some single precision VFP instructions may be executed on both NEON and 1482 // VFP pipelines. 1483} 1484 1485def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 1486 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>, 1487 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1488def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 1489 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>, 1490 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 1491 1492// Match @llvm.fma.* intrinsics 1493// (fma x, y, z) -> (vfms z, x, y) 1494def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)), 1495 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1496 Requires<[HasVFP4,HasDPVFP]>; 1497def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)), 1498 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1499 Requires<[HasVFP4]>; 1500 1501def VFMSD : ADbI<0b11101, 0b10, 1, 0, 1502 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1503 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm", 1504 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 1505 (f64 DPR:$Ddin)))]>, 1506 RegConstraint<"$Ddin = $Dd">, 1507 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1508 1509def VFMSS : ASbIn<0b11101, 0b10, 1, 0, 1510 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1511 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm", 1512 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 1513 SPR:$Sdin))]>, 1514 RegConstraint<"$Sdin = $Sd">, 1515 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> { 1516 // Some single precision VFP instructions may be executed on both NEON and 1517 // VFP pipelines. 1518} 1519 1520def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 1521 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>, 1522 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1523def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 1524 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>, 1525 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 1526 1527// Match @llvm.fma.* intrinsics 1528// (fma (fneg x), y, z) -> (vfms z, x, y) 1529def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)), 1530 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1531 Requires<[HasVFP4,HasDPVFP]>; 1532def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)), 1533 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1534 Requires<[HasVFP4]>; 1535// (fma x, (fneg y), z) -> (vfms z, x, y) 1536def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)), 1537 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1538 Requires<[HasVFP4,HasDPVFP]>; 1539def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)), 1540 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1541 Requires<[HasVFP4]>; 1542 1543def VFNMAD : ADbI<0b11101, 0b01, 1, 0, 1544 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1545 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm", 1546 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 1547 (f64 DPR:$Ddin)))]>, 1548 RegConstraint<"$Ddin = $Dd">, 1549 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1550 1551def VFNMAS : ASbI<0b11101, 0b01, 1, 0, 1552 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1553 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm", 1554 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 1555 SPR:$Sdin))]>, 1556 RegConstraint<"$Sdin = $Sd">, 1557 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> { 1558 // Some single precision VFP instructions may be executed on both NEON and 1559 // VFP pipelines. 1560} 1561 1562def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin), 1563 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>, 1564 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1565def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin), 1566 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>, 1567 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 1568 1569// Match @llvm.fma.* intrinsics 1570// (fneg (fma x, y, z)) -> (vfnma z, x, y) 1571def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))), 1572 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1573 Requires<[HasVFP4,HasDPVFP]>; 1574def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))), 1575 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1576 Requires<[HasVFP4]>; 1577// (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y) 1578def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))), 1579 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1580 Requires<[HasVFP4,HasDPVFP]>; 1581def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))), 1582 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1583 Requires<[HasVFP4]>; 1584 1585def VFNMSD : ADbI<0b11101, 0b01, 0, 0, 1586 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1587 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm", 1588 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm), 1589 (f64 DPR:$Ddin)))]>, 1590 RegConstraint<"$Ddin = $Dd">, 1591 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1592 1593def VFNMSS : ASbI<0b11101, 0b01, 0, 0, 1594 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1595 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm", 1596 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, 1597 RegConstraint<"$Sdin = $Sd">, 1598 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> { 1599 // Some single precision VFP instructions may be executed on both NEON and 1600 // VFP pipelines. 1601} 1602 1603def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin), 1604 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>, 1605 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1606def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin), 1607 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>, 1608 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 1609 1610// Match @llvm.fma.* intrinsics 1611 1612// (fma x, y, (fneg z)) -> (vfnms z, x, y)) 1613def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))), 1614 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1615 Requires<[HasVFP4,HasDPVFP]>; 1616def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))), 1617 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1618 Requires<[HasVFP4]>; 1619// (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y) 1620def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))), 1621 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1622 Requires<[HasVFP4,HasDPVFP]>; 1623def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))), 1624 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1625 Requires<[HasVFP4]>; 1626// (fneg (fma x, (fneg y), z) -> (vfnms z, x, y) 1627def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))), 1628 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1629 Requires<[HasVFP4,HasDPVFP]>; 1630def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))), 1631 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1632 Requires<[HasVFP4]>; 1633 1634//===----------------------------------------------------------------------===// 1635// FP Conditional moves. 1636// 1637 1638let hasSideEffects = 0 in { 1639def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p), 1640 IIC_fpUNA64, 1641 [(set (f64 DPR:$Dd), 1642 (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>, 1643 RegConstraint<"$Dn = $Dd">, Requires<[HasVFP2,HasDPVFP]>; 1644 1645def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p), 1646 IIC_fpUNA32, 1647 [(set (f32 SPR:$Sd), 1648 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>, 1649 RegConstraint<"$Sn = $Sd">, Requires<[HasVFP2]>; 1650} // hasSideEffects 1651 1652//===----------------------------------------------------------------------===// 1653// Move from VFP System Register to ARM core register. 1654// 1655 1656class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, 1657 list<dag> pattern>: 1658 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> { 1659 1660 // Instruction operand. 1661 bits<4> Rt; 1662 1663 let Inst{27-20} = 0b11101111; 1664 let Inst{19-16} = opc19_16; 1665 let Inst{15-12} = Rt; 1666 let Inst{11-8} = 0b1010; 1667 let Inst{7} = 0; 1668 let Inst{6-5} = 0b00; 1669 let Inst{4} = 1; 1670 let Inst{3-0} = 0b0000; 1671} 1672 1673// APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags 1674// to APSR. 1675let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in 1676def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins), 1677 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>; 1678 1679// Application level FPSCR -> GPR 1680let hasSideEffects = 1, Uses = [FPSCR] in 1681def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins), 1682 "vmrs", "\t$Rt, fpscr", 1683 [(set GPR:$Rt, (int_arm_get_fpscr))]>; 1684 1685// System level FPEXC, FPSID -> GPR 1686let Uses = [FPSCR] in { 1687 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins), 1688 "vmrs", "\t$Rt, fpexc", []>; 1689 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins), 1690 "vmrs", "\t$Rt, fpsid", []>; 1691 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins), 1692 "vmrs", "\t$Rt, mvfr0", []>; 1693 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins), 1694 "vmrs", "\t$Rt, mvfr1", []>; 1695 def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPR:$Rt), (ins), 1696 "vmrs", "\t$Rt, mvfr2", []>, Requires<[HasFPARMv8]>; 1697 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins), 1698 "vmrs", "\t$Rt, fpinst", []>; 1699 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins), 1700 "vmrs", "\t$Rt, fpinst2", []>; 1701} 1702 1703//===----------------------------------------------------------------------===// 1704// Move from ARM core register to VFP System Register. 1705// 1706 1707class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, 1708 list<dag> pattern>: 1709 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> { 1710 1711 // Instruction operand. 1712 bits<4> src; 1713 1714 // Encode instruction operand. 1715 let Inst{15-12} = src; 1716 1717 let Inst{27-20} = 0b11101110; 1718 let Inst{19-16} = opc19_16; 1719 let Inst{11-8} = 0b1010; 1720 let Inst{7} = 0; 1721 let Inst{4} = 1; 1722} 1723 1724let Defs = [FPSCR] in { 1725 // Application level GPR -> FPSCR 1726 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src), 1727 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>; 1728 // System level GPR -> FPEXC 1729 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src), 1730 "vmsr", "\tfpexc, $src", []>; 1731 // System level GPR -> FPSID 1732 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src), 1733 "vmsr", "\tfpsid, $src", []>; 1734 1735 def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPR:$src), 1736 "vmsr", "\tfpinst, $src", []>; 1737 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPR:$src), 1738 "vmsr", "\tfpinst2, $src", []>; 1739} 1740 1741//===----------------------------------------------------------------------===// 1742// Misc. 1743// 1744 1745// Materialize FP immediates. VFP3 only. 1746let isReMaterializable = 1 in { 1747def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm), 1748 VFPMiscFrm, IIC_fpUNA64, 1749 "vmov", ".f64\t$Dd, $imm", 1750 [(set DPR:$Dd, vfp_f64imm:$imm)]>, 1751 Requires<[HasVFP3,HasDPVFP]> { 1752 bits<5> Dd; 1753 bits<8> imm; 1754 1755 let Inst{27-23} = 0b11101; 1756 let Inst{22} = Dd{4}; 1757 let Inst{21-20} = 0b11; 1758 let Inst{19-16} = imm{7-4}; 1759 let Inst{15-12} = Dd{3-0}; 1760 let Inst{11-9} = 0b101; 1761 let Inst{8} = 1; // Double precision. 1762 let Inst{7-4} = 0b0000; 1763 let Inst{3-0} = imm{3-0}; 1764} 1765 1766def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm), 1767 VFPMiscFrm, IIC_fpUNA32, 1768 "vmov", ".f32\t$Sd, $imm", 1769 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> { 1770 bits<5> Sd; 1771 bits<8> imm; 1772 1773 let Inst{27-23} = 0b11101; 1774 let Inst{22} = Sd{0}; 1775 let Inst{21-20} = 0b11; 1776 let Inst{19-16} = imm{7-4}; 1777 let Inst{15-12} = Sd{4-1}; 1778 let Inst{11-9} = 0b101; 1779 let Inst{8} = 0; // Single precision. 1780 let Inst{7-4} = 0b0000; 1781 let Inst{3-0} = imm{3-0}; 1782} 1783} 1784 1785//===----------------------------------------------------------------------===// 1786// Assembler aliases. 1787// 1788// A few mnemonic aliases for pre-unifixed syntax. We don't guarantee to 1789// support them all, but supporting at least some of the basics is 1790// good to be friendly. 1791def : VFP2MnemonicAlias<"flds", "vldr">; 1792def : VFP2MnemonicAlias<"fldd", "vldr">; 1793def : VFP2MnemonicAlias<"fmrs", "vmov">; 1794def : VFP2MnemonicAlias<"fmsr", "vmov">; 1795def : VFP2MnemonicAlias<"fsqrts", "vsqrt">; 1796def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">; 1797def : VFP2MnemonicAlias<"fadds", "vadd.f32">; 1798def : VFP2MnemonicAlias<"faddd", "vadd.f64">; 1799def : VFP2MnemonicAlias<"fmrdd", "vmov">; 1800def : VFP2MnemonicAlias<"fmrds", "vmov">; 1801def : VFP2MnemonicAlias<"fmrrd", "vmov">; 1802def : VFP2MnemonicAlias<"fmdrr", "vmov">; 1803def : VFP2MnemonicAlias<"fmuls", "vmul.f32">; 1804def : VFP2MnemonicAlias<"fmuld", "vmul.f64">; 1805def : VFP2MnemonicAlias<"fnegs", "vneg.f32">; 1806def : VFP2MnemonicAlias<"fnegd", "vneg.f64">; 1807def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">; 1808def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">; 1809def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">; 1810def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">; 1811def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">; 1812def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">; 1813def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">; 1814def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">; 1815def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">; 1816def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">; 1817def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">; 1818def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">; 1819def : VFP2MnemonicAlias<"fsts", "vstr">; 1820def : VFP2MnemonicAlias<"fstd", "vstr">; 1821def : VFP2MnemonicAlias<"fmacd", "vmla.f64">; 1822def : VFP2MnemonicAlias<"fmacs", "vmla.f32">; 1823def : VFP2MnemonicAlias<"fcpys", "vmov.f32">; 1824def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">; 1825def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">; 1826def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">; 1827def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">; 1828def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">; 1829def : VFP2MnemonicAlias<"fmrx", "vmrs">; 1830def : VFP2MnemonicAlias<"fmxr", "vmsr">; 1831 1832// Be friendly and accept the old form of zero-compare 1833def : VFP2DPInstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>; 1834def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>; 1835 1836 1837def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>; 1838def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm", 1839 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>; 1840def : VFP2DPInstAlias<"faddd${p} $Dd, $Dn, $Dm", 1841 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>; 1842def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm", 1843 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>; 1844def : VFP2DPInstAlias<"fsubd${p} $Dd, $Dn, $Dm", 1845 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>; 1846 1847// No need for the size suffix on VSQRT. It's implied by the register classes. 1848def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>; 1849def : VFP2DPInstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>; 1850 1851// VLDR/VSTR accept an optional type suffix. 1852def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr", 1853 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>; 1854def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr", 1855 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>; 1856def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr", 1857 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>; 1858def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr", 1859 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>; 1860 1861// VMOV can accept optional 32-bit or less data type suffix suffix. 1862def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn", 1863 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 1864def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn", 1865 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 1866def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn", 1867 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 1868def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt", 1869 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 1870def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt", 1871 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 1872def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt", 1873 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 1874 1875def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn", 1876 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>; 1877def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2", 1878 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>; 1879 1880// VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way 1881// VMOVD does. 1882def : VFP2InstAlias<"vmov${p} $Sd, $Sm", 1883 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>; 1884 1885// FCONSTD/FCONSTS alias for vmov.f64/vmov.f32 1886// These aliases provide added functionality over vmov.f instructions by 1887// allowing users to write assembly containing encoded floating point constants 1888// (e.g. #0x70 vs #1.0). Without these alises there is no way for the 1889// assembler to accept encoded fp constants (but the equivalent fp-literal is 1890// accepted directly by vmovf). 1891def : VFP3InstAlias<"fconstd${p} $Dd, $val", 1892 (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p)>; 1893def : VFP3InstAlias<"fconsts${p} $Sd, $val", 1894 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>; 1895