Lines Matching refs:SPR

93 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
95 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]> {
107 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
109 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]> {
290 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
292 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
306 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
308 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
322 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
324 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
334 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
336 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
348 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
350 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
360 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
362 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
382 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
384 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,
402 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
403 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
413 (outs), (ins SPR:$Sd, SPR:$Sm),
415 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
428 (outs), (ins SPR:$Sd, SPR:$Sm),
447 (outs SPR:$Sd), (ins SPR:$Sm),
449 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
465 (outs), (ins SPR:$Sd),
467 [(arm_cmpfp0 SPR:$Sd)]> {
486 (outs), (ins SPR:$Sd),
499 (outs DPR:$Dd), (ins SPR:$Sm),
501 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
516 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
518 [(set SPR:$Sd, (fround DPR:$Dm))]> {
541 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
546 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
551 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
556 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
562 (outs DPR:$Dd), (ins SPR:$Sm),
574 (outs SPR:$Sd), (ins DPR:$Dm),
589 (outs DPR:$Dd), (ins SPR:$Sm),
601 (outs SPR:$Sd), (ins DPR:$Dm),
615 def : Pat<(fp_to_f16 SPR:$a),
616 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
622 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
625 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
631 (outs SPR:$Sd), (ins SPR:$Sm),
639 (outs SPR:$Sd), (ins SPR:$Sm),
647 (outs SPR:$Sd), (ins DPR:$Dm),
662 (outs SPR:$Sd), (ins DPR:$Dm),
678 def : Pat<(i32 (fp_to_sint (node SPR:$a))),
680 (!cast<Instruction>(NAME#"SS") SPR:$a),
682 def : Pat<(i32 (fp_to_uint (node SPR:$a))),
684 (!cast<Instruction>(NAME#"US") SPR:$a),
710 (outs SPR:$Sd), (ins SPR:$Sm),
712 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
720 (outs SPR:$Sd), (ins SPR:$Sm),
722 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
737 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>,
752 (outs SPR:$Sd), (ins SPR:$Sm),
754 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
768 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm)>,
786 (outs SPR:$Sd), (ins SPR:$Sm),
788 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
796 (outs SPR:$Sd), (ins SPR:$Sm),
805 (outs GPR:$Rt), (ins SPR:$Sn),
807 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
827 (outs SPR:$Sn), (ins GPR:$Rt),
829 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
877 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
899 // FMDHR: GPR -> SPR
900 // FMDLR: GPR -> SPR
946 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
969 // FMRDH: SPR -> GPR
970 // FMRDL: SPR -> GPR
971 // FMRRS: SPR -> GPR
972 // FMRX: SPR system reg -> GPR
973 // FMSRR: GPR -> SPR
1015 (outs DPR:$Dd), (ins SPR:$Sm),
1023 (VSITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1030 (outs SPR:$Sd),(ins SPR:$Sm),
1041 (VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
1047 (outs DPR:$Dd), (ins SPR:$Sm),
1055 (VUITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1062 (outs SPR:$Sd), (ins SPR:$Sm),
1073 (VUITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
1118 (outs SPR:$Sd), (ins DPR:$Dm),
1133 (outs SPR:$Sd), (ins SPR:$Sm),
1143 def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)),
1144 (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;
1146 def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_sint (f32 SPR:$a))),
1148 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;
1151 (outs SPR:$Sd), (ins DPR:$Dm),
1166 (outs SPR:$Sd), (ins SPR:$Sm),
1176 def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)),
1177 (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>;
1179 def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_uint (f32 SPR:$a))),
1181 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;
1187 (outs SPR:$Sd), (ins DPR:$Dm),
1189 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
1194 (outs SPR:$Sd), (ins SPR:$Sm),
1196 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
1201 (outs SPR:$Sd), (ins DPR:$Dm),
1203 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
1208 (outs SPR:$Sd), (ins SPR:$Sm),
1210 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
1253 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1261 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1269 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1277 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1303 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1311 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1319 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1327 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1365 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1367 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1368 SPR:$Sdin))]>,
1379 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1380 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1392 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1394 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1395 SPR:$Sdin))]>,
1406 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1407 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1419 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1421 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1422 SPR:$Sdin))]>,
1433 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1434 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1446 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1448 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1459 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1460 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1475 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1477 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1478 SPR:$Sdin))]>,
1488 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1489 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1497 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
1498 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1510 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1512 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1513 SPR:$Sdin))]>,
1523 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1524 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1532 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
1533 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1539 def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)),
1540 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1552 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1554 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1555 SPR:$Sdin))]>,
1565 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1566 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1574 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
1575 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1581 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
1582 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1594 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1596 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1606 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1607 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1616 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),
1617 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1623 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
1624 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1630 def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))),
1631 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1645 def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
1647 [(set (f32 SPR:$Sd),
1648 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>,
1766 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
1769 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
1834 def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>;
1839 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1843 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1848 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
1853 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1855 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1863 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1865 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1867 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1869 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1871 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1873 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1883 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;
1894 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>;