Lines Matching refs:ImmOp
1260 Operand ImmOp, bits<2>MajOp>
1262 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1342 Operand ImmOp, Operand predImmOp, bits<2> MajOp> {
1345 def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>;
1411 class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
1413 (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
1422 string ImmOpStr = !cast<string>(ImmOp);
1444 class T_StorePI_nv_pred <string mnemonic, Operand ImmOp,
1448 ImmOp:$offset, IntRegs:$src3),
1459 string ImmOpStr = !cast<string>(ImmOp);
1479 multiclass ST_PostInc_Pred_nv<string mnemonic, Operand ImmOp,
1481 def _pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 0>;
1484 def new_pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 1>;
1487 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp,
1490 def S2_#NAME#_pi : T_StorePI_nv <mnemonic, ImmOp, MajOp>;
1493 defm S2_p#NAME#t : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 0>;
1494 defm S2_p#NAME#f : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 1>;
2868 class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
2871 (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
2899 class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
2902 (ins IntRegs:$base, ImmOp:$offset, u5Imm:$delta),
2929 multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
2930 def L4_add#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
2931 def L4_sub#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
2932 def L4_and#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
2933 def L4_or#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
2937 multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
2938 def L4_iadd#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
2939 def L4_isub#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
2940 def L4_iand#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = clrbit(", 0b10>;
2941 def L4_ior#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = setbit(", 0b11>;
2944 multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
2945 defm _#NAME : MemOp_rr <opc, opcBits, ImmOp>;
2946 defm _#NAME : MemOp_ri <opc, opcBits, ImmOp>;
3307 class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3309 : STInst<(outs), (ins ImmOp:$addr, RC:$src),
3316 string ImmOpStr = !cast<string>(ImmOp);
3373 class T_StoreAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3377 string ImmOpStr = !cast<string>(ImmOp);
3394 Operand ImmOp, bits<2> MajOp, bit isHalf = 0> {
3397 def S2_#NAME#abs : T_StoreAbs <mnemonic, RC, ImmOp, MajOp, isHalf>;
3415 class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp, bit isAbs>
3423 string ImmOpStr = !cast<string>(ImmOp);
3476 class T_StoreAbs_NV <string mnemonic, Operand ImmOp, bits<2> MajOp>
3477 : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 1>, AddrModeRel {
3479 string ImmOpStr = !cast<string>(ImmOp);
3495 multiclass ST_Abs_NV <string mnemonic, string CextOp, Operand ImmOp,
3499 def S2_#NAME#newabs : T_StoreAbs_NV <mnemonic, ImmOp, MajOp>;
3541 Operand ImmOp, bits<2> MajOp, bit isHalf = 0>
3542 : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, 0, isHalf> {
3550 multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp,
3556 def NAME#gp : T_StoreAbsGP <mnemonic, IntRegs, ImmOp, MajOp,
3559 def NAME#newgp : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 0> ;
3618 class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3620 : LDInst <(outs RC:$dst), (ins ImmOp:$addr),
3627 string ImmOpStr = !cast<string>(ImmOp);
3644 class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3648 string ImmOpStr = !cast<string>(ImmOp);
3705 Operand ImmOp, bits<3> MajOp> {
3708 def L4_#NAME#_abs: T_LoadAbs <mnemonic, RC, ImmOp, MajOp>;
3740 class T_LoadGP <string mnemonic, string BaseOp, RegisterClass RC, Operand ImmOp,
3742 : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp>, PredNewRel {