Lines Matching refs:Rd
131 let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
245 : ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8Ext:$s8),
246 "$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>,
256 bits<5> Rd;
267 let Inst{4-0} = Rd;
1770 def C4_addipc : CRInst <(outs IntRegs:$Rd), (ins u6Ext:$u6),
1771 "$Rd = add(pc, #$u6)", [], "", CR_tc_2_SLOT3 > {
1772 bits<5> Rd;
1778 let Inst{4-0} = Rd;
1876 def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
1877 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1878 bits<5> Rd;
1886 let Inst{4-0} = Rd;
1890 // Rd=add(Rs,add(Ru,#s6))
1893 def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd),
1895 "$Rd = add($Rs, add($Ru, #$s6))" ,
1896 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs),
1899 bits<5> Rd;
1910 let Inst{12-8} = Rd;
1917 def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd),
1919 "$Rd = add($Rs, sub(#$s6, $Ru))",
1921 bits<5> Rd;
1932 let Inst{12-8} = Rd;
1937 // Rd=add(Rs,sub(#s6,Ru))
1942 // Rd=sub(add(Rs,#s6),Ru)
1947 // Rd=add(sub(Rs,Ru),#s6)
1962 // Rd=extract(Rs,Rtt)
1963 // Rd=extract(Rs,#u5,#U5)
2121 def A4_modwrapu: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
2122 "$Rd = modwrap($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
2123 bits<5> Rd;
2132 let Inst{4-0} = Rd;
2136 def A4_bitsplit: ALU64Inst<(outs DoubleRegs:$Rd),
2138 "$Rd = bitsplit($Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
2139 bits<5> Rd;
2148 let Inst{4-0} = Rd;
2152 def dep_S2_packhl: ALU64Inst<(outs DoubleRegs:$Rd),
2154 "$Rd = packhl($Rs, $Rt):deprecated", [], "", ALU64_tc_1_SLOT23> {
2155 bits<5> Rd;
2164 let Inst{4-0} = Rd;
2168 def dep_A2_addsat: ALU64Inst<(outs IntRegs:$Rd),
2170 "$Rd = add($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> {
2171 bits<5> Rd;
2180 let Inst{4-0} = Rd;
2184 def dep_A2_subsat: ALU64Inst<(outs IntRegs:$Rd),
2186 "$Rd = sub($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> {
2187 bits<5> Rd;
2196 let Inst{4-0} = Rd;
2271 // Rd=modwrap(Rs,Rt)
2273 // Rd=cround(Rs,#u5)
2274 // Rd=cround(Rs,Rt)
2275 // Rd=round(Rs,#u5)[:sat]
2276 // Rd=round(Rs,Rt)[:sat]
2278 // Rd=vraddh(Rss,Rtt)
2339 def S4_clbaddi : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s6Imm:$s6),
2340 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
2342 bits<5> Rd;
2350 let Inst{4-0} = Rd;
2354 def S4_clbpaddi : SInst<(outs IntRegs:$Rd), (ins DoubleRegs:$Rs, s6Imm:$s6),
2355 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
2357 bits<5> Rd;
2365 let Inst{4-0} = Rd;
2416 // Rd=add(#u6,mpyi(Rs,#U6)) -- Multiply by immed and add immed.
2419 def M4_mpyri_addi : MInst<(outs IntRegs:$Rd),
2421 "$Rd = add(#$u6, mpyi($Rs, #$U6))" ,
2422 [(set (i32 IntRegs:$Rd),
2425 bits<5> Rd;
2437 let Inst{12-8} = Rd;
2442 // Rd=add(#u6,mpyi(Rs,Rt))
2445 def M4_mpyrr_addi : MInst <(outs IntRegs:$Rd),
2447 "$Rd = add(#$u6, mpyi($Rs, $Rt))" ,
2448 [(set (i32 IntRegs:$Rd),
2451 bits<5> Rd;
2464 let Inst{4-0} = Rd;
2630 : MInst_acc<(outs IntRegs:$Rd), (ins u8Ext:$u8, IntRegs:$Rx, u5Imm:$U5),
2631 "$Rd = "#MnOp#"(#$u8, "#MnSh#"($Rx, #$U5))",
2632 [(set (i32 IntRegs:$Rd),
2634 "$Rd = $Rx", Itin> {
2636 bits<5> Rd;
2644 let Inst{20-16} = Rd;
2685 // Rd=[cround|round](Rs,Rt)
2691 // Rd=round(Rs,Rt):sat
2695 // Rd=[cmpyiwh|cmpyrwh](Rss,Rt):<<1:rnd:sat
2768 def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6Imm:$s6, IntRegs:$Rt),
2769 "$Rd = lsl(#$s6, $Rt)" ,
2770 [(set (i32 IntRegs:$Rd), (shl s6ImmPred:$s6,
2773 bits<5> Rd;
2783 let Inst{4-0} = Rd;
3767 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
4214 (outs IntRegs:$Rd),
4216 "$Rd = #$U6 ; jump $r9_2"> {
4217 bits<4> Rd;
4224 let Inst{19-16} = Rd;
4234 (outs IntRegs:$Rd),
4236 "$Rd = $Rs ; jump $r9_2"> {
4237 bits<4> Rd;
4244 let Inst{11-8} = Rd;