Lines Matching refs:BaseReg
60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is16BitMemOperand() local
64 if (is16BitMode(STI) && BaseReg.getReg() == 0 && in Is16BitMemOperand()
67 if ((BaseReg.getReg() != 0 && in Is16BitMemOperand()
68 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || in Is16BitMemOperand()
226 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is32BitMemOperand() local
229 if ((BaseReg.getReg() != 0 && in Is32BitMemOperand()
230 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || in Is32BitMemOperand()
241 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is64BitMemOperand() local
244 if ((BaseReg.getReg() != 0 && in Is64BitMemOperand()
245 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || in Is64BitMemOperand()
372 unsigned BaseReg = Base.getReg(); in EmitMemModRMByte() local
376 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode in EmitMemModRMByte()
401 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U; in EmitMemModRMByte()
406 if (BaseReg) { in EmitMemModRMByte()
476 (!is64BitMode(STI) || BaseReg != 0)) { in EmitMemModRMByte()
478 if (BaseReg == 0) { // [disp32] in X86-32 mode in EmitMemModRMByte()
526 if (BaseReg == 0) { in EmitMemModRMByte()
559 if (BaseReg == 0) { in EmitMemModRMByte()