Lines Matching refs:cpu
3 * or1korbis.cpu (l-msync, l-psync, l-csync): New instructions.
11 * or1korbis.cpu (h-atomic-reserve): New hardware.
23 * openrisc.cpu: Delete.
25 * or1k.cpu: New file.
27 * or1kcommon.cpu: New file.
28 * or1korbis.cpu: New file.
29 * or1korfpx.cpu: New file.
38 * lm32.cpu (Control and status registers): Add CFG2, PSW,
44 * epiphany.cpu (keyword gr-names): Move sb/sl/ip after r9/r10/r12.
76 * cpu/epiphany.cpu: New file.
77 * cpu/epiphany.opc: New file.
81 * fr30.cpu: Newly contributed file.
83 * ip2k.cpu: Likewise.
85 * mep-avc.cpu: Likewise.
86 * mep-avc2.cpu: Likewise.
87 * mep-c5.cpu: Likewise.
88 * mep-core.cpu: Likewise.
89 * mep-default.cpu: Likewise.
90 * mep-ext-cop.cpu: Likewise.
91 * mep-fmax.cpu: Likewise.
92 * mep-h1.cpu: Likewise.
93 * mep-ivc2.cpu: Likewise.
94 * mep-rhcop.cpu: Likewise.
95 * mep-sample-ucidsp.cpu: Likewise.
96 * mep.cpu: Likewise.
98 * openrisc.cpu: Likewise.
100 * xstormy16.cpu: Likewise.
109 * m32c.cpu (f-dsp-8-s24): Mask high byte after shifting it.
113 * m32r.cpu (HASH-PREFIX): Delete.
122 * xc16x.cpu (dowh): New pmacro.
132 * frv.cpu (floating-point-conversion): Update call to fp conv op.
139 * m32c.cpu (f-dsp-32-u24): Fix mode of extract handler.
154 * xc16x.cpu (mov4): Fix mode of `sequence'.
169 * m32r.cpu (stb-plus): Typo fix.
173 * m32r.cpu (sth-plus): Fix address mode and calculation.
178 * xc16x.cpu (rtl-version): Set to 0.8.
192 * cpu/simplify.inc (*): One line doc strings don't need \n.
203 * frv.cpu (mabshs): Explicitly sign-extend arguments of abs to DI.
210 * cris.cpu (cris-implemented-writable-specregs-v32): Correct size
215 * lm32.cpu: New file.
225 * cris.cpu (movs, movu): Use result of extension operation when
230 * cris.cpu: Update copyright notice to refer to GPLv3.
231 * frv.cpu, frv.opc, iq10.cpu, iq2000m.cpu, iq2000.opc, m32c.cpu,
232 m32c.opc, m32r.cpu, m32r.opc, mt.cpu, mt.opc, sh64-compact.cpu,
233 sh64-media.cpu, sh.cpu, sh.opc, simplify.inc, xc16x.cpu,
235 * iq2000.cpu: Fix copyright notice to refer to FSF.
239 * frv.cpu (spr-names): Support new coprocessor SPR registers.
243 * xc16x.cpu: Restore after accidentally overwriting this file with
248 * m32c.cpu (Imm-8-s4n): Fix print hook.
255 * m32c.cpu (f-dsp-40-u20, f-dsp-48-u20, Dsp-40-u20, Dsp-40-u20,
271 * iq2000.cpu: Fix include paths for iq2000m.cpu and iq10.cpu.
289 * m32c.cpu (Bit3-S): New.
293 * m32c.cpu (decimal-subtraction16-insn): Add second operand.
301 * m32c.cpu (mul.l): New.
313 * m32c.cpu (RL_TYPE): New attribute, with macros.
328 * xc16x.cpu: New file containing complete CGEN specific XC16X CPU
338 * m32c.cpu (mov.w:q): Fix mode.
344 * mt.cpu (define-arch, define-isa): Set name to mt.
352 * m32c.cpu (jsri): Fix order so register names aren't treated as
359 * mt.cpu: Rename from ms1.cpu.
364 * cris.cpu (simplecris-common-writable-specregs)
384 * ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and
415 * m32c.cpu (Imm-8-s4n, Imm-12-s4n): New.
430 * m32c.cpu (f-dsp-8-s24, Dsp-8-s24): New.
445 * m32c.cpu (add16-bQ-sp,add16-wQ-sp): Fix to allow either width by
450 * m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing.
467 * cpu/m32r.opc (parse_slo16): Do not assume a 32-bit host word
480 * m32c.cpu (f-16-8, f-24-8, f-32-16, f-dsp-8-u24): New opcode
509 * m32c.cpu, m32c.opc: Fix copyright.
513 * m32c.cpu, m32c.opc: Machine description for the Renesas M32C.
521 * iq2000.cpu: Include from binutils cpu dir.
543 * ms1.cpu: New file. Written by Nick Clifton, Stan Cox.
550 cris.cpu, frv.cpu, frv.opc, iq10.cpu, iq2000.opc, iq2000m.cpu,
551 m32r.cpu, m32r.opc, sh.cpu, sh.opc, sh64-compact.cpu,
552 sh64-media.cpu, simplify.inc
571 * cris.cpu (mstep): Add missing insn.
576 * frv.cpu: Add support for TLS annotations in loads and calll.
589 * cris.cpu (cris-set-mem): Correct integral write semantics.
593 * cris.cpu: New file.
597 * iq2000.cpu: Added quotes around macro arguments so that they
602 * iq2000m.cpu (pkrlr1, pkrlr30, rbr1, rbr30, rxr1, rxr30, wbr1,
605 * iq2000.cpu (dnop index): Rename to _index to avoid complications
610 * frv.cpu (cfmovs): Change UNIT attribute to FMALL.
622 * frv.cpu (define-arch frv): Add fr450 mach.
654 * frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit.
665 * frv.cpu (r-store, r-store-dual, r-store-quad): Delete.
675 * cpu/m32r.opc (my_print_insn): Fixed incorrect output when
680 * cpu/m32r.cpu: Add PIPE_O attribute to "pop" instruction.
684 * cpu/m32r.cpu : Add new model m32r2.
689 * cpu/m32r.opc (CGEN_DIS_HASH, my_print_insn):
695 * m32r.opc, m32r.cpu: New files. Written by , Doug Evans, Nick
698 * sh.cpu, sh.opc, sh64-compact.cpu, sh64-media.cpu: New files, all
703 * frv.cpu (UNIT): Add IACC.
728 * frv.cpu (dnpmop): New p-macro.
741 * frv.cpu, frv.opc: Add support for fr550.
745 * frv.cpu (u-commit): New modelling unit for fr500.
755 * frv.cpu (nldqi): Delete unimplemented instruction.
759 * frv.cpu (u-clrgr, u-clrfr): New units of model fr500.
767 * frv.cpu: Typographical corrections.
771 * frv.cpu (media-dual-complex): Change UNIT to FMALL.
776 * frv.cpu (register-transfer): Pass in all attributes in on argument.
792 * frv.cpu (UNIT): Add IALL, FMALL, FMLOW, STORE, SCAN, DCPL, MDUALACC,
803 * frv.cpu (mbtoh): Replace input parameter to u-media-dual-expand
809 * frv.cpu: Fix typo, Frintkeven -> FRintkeven
813 * frv.cpu: Add IDOC attribute.
818 * iq2000.cpu: New file. Written by Ben Elliston, Jeff Johnston,
822 * iq2000m.cpu: New file. Written by Jeff Johnston.
823 * iq10.cpu: New file. Written by Jeff Johnston.
827 * frv.cpu (FRintieven): New operand. An even-numbered only
851 * frv.cpu (media-dual-word-rotate-r-r): Use a signed 6-bit
857 * frv.cpu: New file. Written by Dave Brolley, Catherine Moore,