Lines Matching refs:comment

30   (comment "Hitachi SuperH (SH)")
41   (comment "SHmedia 32-bit instruction set")
47   (comment "SHcompact 16-bit instruction set")
56   (comment "SH 64-bit family")
64   (comment "SH-2 CPU core")
71   (comment "SH-3 CPU core")
78   (comment "SH-3e CPU core")
85   (comment "SH-4 CPU core")
92   (comment "SH-5 CPU core")
99   (comment "SH-5 reference implementation")
110   (comment "Program counter")
123   (comment "General purpose integer registers")
139   (comment "General purpose integer registers (SHcompact view)")
153   (comment "Control registers")
169   (comment "Status register")
176   (comment "Floating point status and control register")
183   (comment "Floating point register file bit")
192   (comment "Floating point transfer size bit")
201   (comment "Floating point precision bit")
210   (comment "Multiply-accumulate saturation flag")
219   (comment "Divide-step M flag")
228   (comment "Divide-step Q flag")
239   (comment "Single precision floating point registers")
250   (comment "Single precision floating point register pairs")
260   (comment "Single precision floating point vectors")
271   (comment "Single precision floating point matrices")
284   (comment "Double precision floating point registers")
303   (comment "Branch target registers")
311   (comment "Current endian mode")
320   (comment "Current instruction set mode")