1; Hitachi SH architecture description.  -*- Scheme -*-
2;
3; Copyright 2000, 2001, 2007, 2009 Free Software Foundation, Inc.
4;
5; Contributed by Red Hat Inc; developed under contract from Hitachi
6; Semiconductor (America) Inc.
7;
8; This file is part of the GNU Binutils.
9;
10; This program is free software; you can redistribute it and/or modify
11; it under the terms of the GNU General Public License as published by
12; the Free Software Foundation; either version 3 of the License, or
13; (at your option) any later version.
14;
15; This program is distributed in the hope that it will be useful,
16; but WITHOUT ANY WARRANTY; without even the implied warranty of
17; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18; GNU General Public License for more details.
19;
20; You should have received a copy of the GNU General Public License
21; along with this program; if not, write to the Free Software
22; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
23; MA 02110-1301, USA.
24
25
26(include "simplify.inc")
27
28(define-arch
29  (name sh)
30  (comment "Hitachi SuperH (SH)")
31  (insn-lsb0? #t)
32  (machs sh2 sh3 sh3e sh4 sh5)
33  (isas compact media)
34)
35
36
37; Instruction sets.
38
39(define-isa
40  (name media)
41  (comment "SHmedia 32-bit instruction set")
42  (base-insn-bitsize 32)
43)
44
45(define-isa
46  (name compact)
47  (comment "SHcompact 16-bit instruction set")
48  (base-insn-bitsize 16)
49)
50
51
52; CPU family.
53
54(define-cpu
55  (name sh64)
56  (comment "SH 64-bit family")
57  (endian either)
58  (word-bitsize 32)
59)
60
61
62(define-mach
63  (name sh2)
64  (comment "SH-2 CPU core")
65  (cpu sh64)
66  (isas compact)
67)
68
69(define-mach
70  (name sh3)
71  (comment "SH-3 CPU core")
72  (cpu sh64)
73  (isas compact)
74)
75
76(define-mach
77  (name sh3e)
78  (comment "SH-3e CPU core")
79  (cpu sh64)
80  (isas compact)
81)
82
83(define-mach
84  (name sh4)
85  (comment "SH-4 CPU core")
86  (cpu sh64)
87  (isas compact)
88)
89
90(define-mach
91  (name sh5)
92  (comment "SH-5 CPU core")
93  (cpu sh64)
94  (isas compact media)
95)
96
97(define-model
98  (name sh5)
99  (comment "SH-5 reference implementation")
100  (mach sh5)
101  (unit u-exec "Execution unit" ()
102	1 1 ; issue done
103	() () () ())
104)
105
106; Hardware elements.
107
108(define-hardware
109  (name h-pc)
110  (comment "Program counter")
111  (attrs PC (ISA compact,media))
112  (type pc UDI)
113  (get () (raw-reg h-pc))
114  (set (newval) (sequence ()
115			  (set (raw-reg h-ism) (and newval 1))
116			  (set (raw-reg h-pc) (and newval (inv UDI 1)))))
117)
118
119(define-pmacro (-build-greg-name n) ((.sym r n) n))
120
121(define-hardware
122  (name h-gr)
123  (comment "General purpose integer registers")
124  (attrs (ISA media,compact))
125  (type register DI (64))
126  (indices keyword "" (.map -build-greg-name (.iota 64)))
127  (get (index)
128       (if DI (eq index 63)
129	   (const 0)
130	   (raw-reg h-gr index)))
131  (set (index newval)
132       (if (ne index 63)
133	   (set (raw-reg h-gr index) newval)
134	   (nop)))
135)
136
137(define-hardware
138  (name h-grc)
139  (comment "General purpose integer registers (SHcompact view)")
140  (attrs VIRTUAL (ISA compact))
141  (type register SI (16))
142  (indices keyword "" (.map -build-greg-name (.iota 16)))
143  (get (index)
144	(and (raw-reg h-gr index) (zext DI #xFFFFFFFF)))
145  (set (index newval)
146       (set (raw-reg h-gr index) (ext DI newval)))
147)
148
149(define-pmacro (-build-creg-name n) ((.sym cr n) n))
150
151(define-hardware
152  (name h-cr)
153  (comment "Control registers")
154  (attrs (ISA media))
155  (type register DI (64))
156  (indices keyword "" (.map -build-creg-name (.iota 64)))
157  (get (index)
158       (if DI (eq index 0)
159	   (zext DI (reg h-sr))
160	   (raw-reg h-cr index)))
161  (set (index newval)
162       (if (eq index 0)
163	   (set (reg h-sr) newval)
164	   (set (raw-reg h-cr index) newval)))
165)
166
167(define-hardware
168  (name h-sr)
169  (comment "Status register")
170  (attrs (ISA compact,media))
171  (type register SI)
172)
173
174(define-hardware
175  (name h-fpscr)
176  (comment "Floating point status and control register")
177  (attrs (ISA compact,media))
178  (type register SI)
179)
180
181(define-hardware
182  (name h-frbit)
183  (comment "Floating point register file bit")
184  (attrs (ISA media,compact) VIRTUAL)
185  (type register BI)
186  (get () (and (srl (reg h-sr) 14) 1))
187  (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 14))) (sll SI newvalue 14))))
188)
189
190(define-hardware
191  (name h-szbit)
192  (comment "Floating point transfer size bit")
193  (attrs (ISA media,compact) VIRTUAL)
194  (type register BI)
195  (get () (and (srl (reg h-sr) 13) 1))
196  (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 13))) (sll SI newvalue 13))))
197)
198
199(define-hardware
200  (name h-prbit)
201  (comment "Floating point precision bit")
202  (attrs (ISA media,compact) VIRTUAL)
203  (type register BI)
204  (get () (and (srl (reg h-sr) 12) 1))
205  (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 12))) (sll SI newvalue 12))))
206)
207
208(define-hardware
209  (name h-sbit)
210  (comment "Multiply-accumulate saturation flag")
211  (attrs (ISA compact) VIRTUAL)
212  (type register BI)
213  (get () (and (srl (reg h-sr) 1) 1))
214  (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv 2)) (sll SI newvalue 1))))
215)
216
217(define-hardware
218  (name h-mbit)
219  (comment "Divide-step M flag")
220  (attrs (ISA compact) VIRTUAL)
221  (type register BI)
222  (get () (and (srl (reg h-sr) 9) 1))
223  (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 9))) (sll SI newvalue 9))))
224)
225
226(define-hardware
227  (name h-qbit)
228  (comment "Divide-step Q flag")
229  (attrs (ISA compact) VIRTUAL)
230  (type register BI)
231  (get () (and (srl (reg h-sr) 8) 1))
232  (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 8))) (sll SI newvalue 8))))
233)
234
235(define-pmacro (-build-freg-name n) ((.sym fr n) n))
236
237(define-hardware
238  (name h-fr)
239  (comment "Single precision floating point registers")
240  (attrs (ISA media,compact))
241  (type register SF (64))
242  (indices keyword "" (.map -build-freg-name (.iota 64)))
243)
244
245
246(define-pmacro (-build-fpair-name n) ((.sym fp n) n))
247
248(define-hardware
249  (name h-fp)
250  (comment "Single precision floating point register pairs")
251  (attrs (ISA media,compact))
252  (type register DF (32))
253  (indices keyword "" (.map -build-fpair-name (.iota 32)))
254)
255
256(define-pmacro (-build-fvec-name n) ((.sym fv n) n))
257
258(define-hardware
259  (name h-fv)
260  (comment "Single precision floating point vectors")
261  (attrs VIRTUAL (ISA media,compact))
262  (type register SF (16))
263  (indices keyword "" (.map -build-fvec-name (.iota 16)))
264  ; Mask with $F to ensure 0 <= index < 15.
265  (get (index) (reg h-fr (mul (and UQI index 15) 4)))
266  (set (index newval) (set (reg h-fr (mul (and UQI index 15) 4)) newval))
267)
268
269(define-hardware
270  (name h-fmtx)
271  (comment "Single precision floating point matrices")
272  (attrs VIRTUAL (ISA media))
273  (type register SF (4))
274  (indices keyword "" ((mtrx0 0) (mtrx1 1) (mtrx2 2) (mtrx3 3)))
275  ; Mask with $3 to ensure 0 <= index < 4.
276  (get (index) (reg h-fr (mul (and UQI index 3) 16)))
277  (set (index newval) (set (reg h-fr (mul (and UQI index 3) 16)) newval))
278)
279
280(define-pmacro (-build-dreg-name n) ((.sym dr n) n))
281
282(define-hardware
283  (name h-dr)
284  (comment "Double precision floating point registers")
285  (attrs (ISA media,compact) VIRTUAL)
286  (type register DF (32))
287  (indices keyword "" (.map -build-dreg-name (.iota 64)))
288  (get (index)
289       (subword DF
290		(or
291		 (sll DI (zext DI (subword SI (reg h-fr index) 0)) 32)
292		 (zext DI (subword SI (reg h-fr (add index 1)) 0))) 0))
293  (set (index newval)
294       (sequence ()
295		 (set (reg h-fr index)
296		      (subword SF (subword SI newval 0) 0))
297		 (set (reg h-fr (add index 1))
298		      (subword SF (subword SI newval 1) 0))))
299)
300
301(define-hardware
302  (name h-tr)
303  (comment "Branch target registers")
304  (attrs (ISA media))
305  (type register DI (8))
306  (indices keyword "" ((tr0 0) (tr1 1) (tr2 2) (tr3 3) (tr4 4) (tr5 5) (tr6 6) (tr7 7)))
307)
308
309(define-hardware
310  (name h-endian)
311  (comment "Current endian mode")
312  (attrs (ISA compact,media) VIRTUAL)
313  (type register BI)
314  (get () (c-call BI "sh64_endian"))
315  (set (newval) (error "cannot alter target byte order mid-program"))
316)
317
318(define-hardware
319  (name h-ism)
320  (comment "Current instruction set mode")
321  (attrs (ISA compact,media))
322  (type register BI)
323  (get () (raw-reg h-ism))
324  (set (newval) (error "cannot set ism directly"))
325)
326
327
328; Operands.
329
330(dnop endian "Endian mode" ((ISA compact,media)) h-endian f-nil)
331(dnop ism    "Instruction set mode" ((ISA compact,media)) h-ism f-nil)
332
333; Universally useful macros.
334
335; A pmacro for use in semantic bodies of unimplemented insns.
336(define-pmacro (unimp mnemonic) (nop))
337
338; Join 2 ints together in natural bit order.
339(define-pmacro (-join-si s1 s0)
340  (or (sll (zext DI s1) 32)
341      (zext DI s0)))
342
343; Join 4 half-ints together in natural bit order.
344(define-pmacro (-join-hi h3 h2 h1 h0)
345  (or (sll (zext DI h3) 48)
346      (or (sll (zext DI h2) 32)
347	  (or (sll (zext DI h1) 16)
348	      (zext DI h0)))))
349
350; Join 8 quarter-ints together in natural bit order.
351(define-pmacro (-join-qi b7 b6 b5 b4 b3 b2 b1 b0)
352  (or (sll (zext DI b7) 56)
353      (or (sll (zext DI b6) 48)
354	  (or (sll (zext DI b5) 40)
355	      (or (sll (zext DI b4) 32)
356		  (or (sll (zext DI b3) 24)
357		      (or (sll (zext DI b2) 16)
358			  (or (sll (zext DI b1) 8)
359			      (zext DI b0)))))))))
360
361
362; Include the two instruction set descriptions from their respective
363; source files.
364
365(if (keep-isa? (compact))
366    (include "sh64-compact.cpu"))
367
368(if (keep-isa? (media))
369    (include "sh64-media.cpu"))
370