| /external/llvm/lib/CodeGen/ |
| D | TargetSchedule.cpp | 128 unsigned DefIdx = 0; in findDefIdx() local
188 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
228 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
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| D | TargetInstrInfo.cpp | 983 SDNode *DefNode, unsigned DefIdx, in getOperandLatency()
1073 const MachineInstr *DefMI, unsigned DefIdx, in getOperandLatency()
1110 const MachineInstr *DefMI, unsigned DefIdx, in computeOperandLatency()
1139 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceInputs()
1164 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregInputs()
1187 const MachineInstr &MI, unsigned DefIdx, in getInsertSubregInputs()
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| D | LiveRangeCalc.cpp | 46 SlotIndex DefIdx = in createDeadDef() local
179 unsigned DefIdx; in extendToUses() local
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| D | LiveRangeEdit.cpp | 126 SlotIndex DefIdx; in canRematerializeAt() local
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| D | MachineInstr.cpp | 815 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); in addOperand() local
1098 unsigned DefIdx; in getRegClassConstraint() local
1291 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { in tieOperands()
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| D | TargetRegisterInfo.cpp | 306 unsigned SrcIdx, DefIdx; in shareSameRegisterFile() local
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| D | PeepholeOptimizer.cpp | 296 unsigned DefIdx; member in __anon2734e12b0111::ValueTracker
369 ValueTracker(const MachineInstr &MI, unsigned DefIdx, unsigned DefSubReg, in ValueTracker()
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| D | MachineVerifier.cpp | 907 unsigned DefIdx; in visitMachineOperand() local
1159 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI); in checkLiveness() local
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| D | RegisterCoalescer.cpp | 661 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); in removeCopyByCommutingDef() local
770 SlotIndex DefIdx = UseIdx.getRegSlot(); in removeCopyByCommutingDef() local
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| D | RegAllocFast.cpp | 743 unsigned DefIdx = 0; in handleThroughOperands() local
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| D | InlineSpiller.cpp | 916 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewVReg, RM, in reMaterializeFor() local
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| D | MachineLICM.cpp | 976 unsigned DefIdx, unsigned Reg) const { in HasHighOperandLatency()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 124 SDNode *DefNode, unsigned DefIdx, in getOperandLatency()
132 unsigned DefIdx) const override { in hasLowDefLatency()
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| D | PPCVSXSwapRemoval.cpp | 617 int DefIdx = SwapMap[DefMI]; in formWebs() local
695 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
751 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
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| D | PPCInstrInfo.cpp | 141 const MachineInstr *DefMI, unsigned DefIdx, in getOperandLatency()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.h | 131 unsigned DefIdx; variable
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| D | ScheduleDAGSDNodes.cpp | 634 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency() local
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| D | InstrEmitter.cpp | 1005 unsigned DefIdx = GroupIdx[DefGroup] + 1; in EmitSpecialNode() local
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrItineraries.h | 186 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding()
207 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency()
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| D | MCSubtargetInfo.h | 128 unsigned DefIdx) const { in getWriteLatencyEntry()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 3154 unsigned DefIdx, unsigned DefAlign) const { in getVLDMDefCycle()
3195 unsigned DefIdx, unsigned DefAlign) const { in getLDMDefCycle()
3298 unsigned DefIdx, unsigned DefAlign, in getOperandLatency()
3409 unsigned &DefIdx, unsigned &Dist) { in getBundledDefMI()
3644 const MachineInstr *DefMI, unsigned DefIdx, in getOperandLatency()
3734 SDNode *DefNode, unsigned DefIdx, in getOperandLatency()
4038 const MachineInstr *DefMI, unsigned DefIdx, in hasHighOperandLatency()
4565 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs()
4590 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregLikeInputs()
4611 const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, in getInsertSubregLikeInputs()
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 891 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs()
905 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregLikeInputs()
919 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, in getInsertSubregLikeInputs()
1206 const MachineInstr *DefMI, unsigned DefIdx, in hasHighOperandLatency()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 206 unsigned DefIdx = 0; in SelectInlineAsm() local
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| /external/llvm/lib/MC/MCDisassembler/ |
| D | Disassembler.cpp | 203 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; in getLatency() local
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| /external/llvm/lib/CodeGen/MIRParser/ |
| D | MIParser.cpp | 887 unsigned DefIdx = Operands[I].TiedDefIdx.getValue(); in assignRegisterTies() local
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