| /external/llvm/lib/CodeGen/ |
| D | RegisterPressure.cpp | 62 for (unsigned Reg : LiveInRegs) in dump() local
66 for (unsigned Reg : LiveOutRegs) in dump() local
174 static const LiveRange *getLiveRange(const LiveIntervals &LIS, unsigned Reg) { in getLiveRange()
301 for (unsigned Reg : P.LiveOutRegs) { in initLiveThru() local
363 unsigned Reg = MO.getReg(); in collectOperand() local
375 void pushRegUnits(unsigned Reg, SmallVectorImpl<unsigned> &RegUnits) const { in pushRegUnits()
405 unsigned Reg = *RI; in detectDeadDefs() local
476 for (unsigned Reg : RegOpers.Defs) in collectPDiff() local
479 for (unsigned Reg : RegOpers.Uses) in collectPDiff() local
485 for (unsigned Reg : Regs) { in addLiveRegs() local
[all …]
|
| D | AggressiveAntiDepBreaker.cpp | 60 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { in GetGroup()
73 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local
95 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) in LeaveGroup()
106 bool AggressiveAntiDepState::IsLive(unsigned Reg) in IsLive()
154 unsigned Reg = *AI; in StartBlock() local
167 unsigned Reg = *I; in StartBlock() local
197 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe() local
223 unsigned Reg = MO.getReg(); in IsImplicitDefUse() local
243 const unsigned Reg = MO.getReg(); in GetPassthruRegs() local
289 void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx, in HandleLastUse()
[all …]
|
| D | LiveVariables.cpp | 182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) { in HandleVirtRegDef()
192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, in FindLastPartialDef()
231 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { in HandlePhysRegUse()
281 MachineInstr *LiveVariables::FindLastRefOrPartRef(unsigned Reg) { in FindLastRefOrPartRef()
311 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) { in HandlePhysRegKill()
426 for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) { in HandleRegMask() local
443 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI, in HandlePhysRegDef()
489 unsigned Reg = Defs.back(); in UpdatePhysRegDefs() local
657 const unsigned Reg = TargetRegisterInfo::index2VirtReg(i); in runOnMachineFunction() local
682 void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr *OldMI, in replaceKillInstruction()
[all …]
|
| D | CriticalAntiDepBreaker.cpp | 62 unsigned Reg = *AI; in StartBlock() local
77 unsigned Reg = *AI; in StartBlock() local
103 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe() local
175 unsigned Reg = MO.getReg(); in PrescanInstruction() local
261 unsigned Reg = MO.getReg(); in ScanInstruction() local
289 unsigned Reg = MO.getReg(); in ScanInstruction() local
451 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { in BreakAntiDependencies() local
600 unsigned Reg = MO.getReg(); in BreakAntiDependencies() local
|
| D | LivePhysRegs.cpp | 50 unsigned Reg = O->getReg(); in stepBackward() local
62 unsigned Reg = O->getReg(); in stepBackward() local
78 unsigned Reg = O->getReg(); in stepForward() local
96 for (auto Reg : Clobbers) { in stepForward() local
|
| D | MachineInstrBundle.cpp | 145 unsigned Reg = MO.getReg(); in finalizeBundle() local
168 unsigned Reg = MO.getReg(); in finalizeBundle() local
199 unsigned Reg = LocalDefs[i]; in finalizeBundle() local
209 unsigned Reg = ExternUses[i]; in finalizeBundle() local
264 MachineOperandIteratorBase::analyzeVirtReg(unsigned Reg, in analyzeVirtReg()
293 MachineOperandIteratorBase::analyzePhysReg(unsigned Reg, in analyzePhysReg()
|
| D | InlineSpiller.cpp | 158 bool isRegToSpill(unsigned Reg) { in isRegToSpill()
213 static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) { in isFullCopyOf()
227 unsigned Reg = Edit->getReg(); in isSnippet() local
271 unsigned Reg = Edit->getReg(); in collectRegsToSpill() local
313 bool InlineSpiller::isSibling(unsigned Reg) { in isSibling()
513 unsigned Reg; in traceSiblingValue() local
658 unsigned Reg = RegsToSpill[i]; in analyzeSiblingValues() local
768 unsigned Reg = LI->reg; in eliminateRedundantSpills() local
948 unsigned Reg = RegsToSpill[i]; in reMaterializeAll() local
967 unsigned Reg = RegsToSpill[i]; in reMaterializeAll() local
[all …]
|
| D | MachineInstr.cpp | 56 void MachineOperand::setReg(unsigned Reg) { in setReg()
76 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, in substVirtReg()
86 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) { in substPhysReg()
176 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, in ChangeToRegister()
975 unsigned Reg = MO.getReg(); in eraseFromParentAndMarkDBGValuesForRemoval() local
1120 unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, in getRegClassConstraintEffectForVReg()
1137 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC, in getRegClassConstraintEffectForVRegImpl()
1179 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, in findRegisterUseOperandIdx()
1203 MachineInstr::readsWritesVirtualRegister(unsigned Reg, in readsWritesVirtualRegister()
1232 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap, in findRegisterDefOperandIdx()
[all …]
|
| D | DeadMachineInstructionElim.cpp | 75 unsigned Reg = MO.getReg(); in isDead() local
141 unsigned Reg = MO.getReg(); in runOnMachineFunction() local
160 unsigned Reg = MO.getReg(); in runOnMachineFunction() local
|
| D | RegisterScavenging.cpp | 34 void RegScavenger::setRegUsed(unsigned Reg, LaneBitmask LaneMask) { in setRegUsed()
95 void RegScavenger::addRegUnits(BitVector &BV, unsigned Reg) { in addRegUnits()
129 unsigned Reg = MO.getReg(); in determineKillsAndDefs() local
201 unsigned Reg = MO.getReg(); in forward() local
254 bool RegScavenger::isRegUsed(unsigned Reg, bool includeReserved) const { in isRegUsed()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 236 inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const { in reg_operands()
252 reg_instructions(unsigned Reg) const { in reg_instructions()
267 inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const { in reg_bundles()
287 reg_nodbg_operands(unsigned Reg) const { in reg_nodbg_operands()
304 reg_nodbg_instructions(unsigned Reg) const { in reg_nodbg_instructions()
321 reg_nodbg_bundles(unsigned Reg) const { in reg_nodbg_bundles()
339 inline iterator_range<def_iterator> def_operands(unsigned Reg) const { in def_operands()
355 def_instructions(unsigned Reg) const { in def_instructions()
370 inline iterator_range<def_bundle_iterator> def_bundles(unsigned Reg) const { in def_bundles()
395 inline iterator_range<use_iterator> use_operands(unsigned Reg) const { in use_operands()
[all …]
|
| D | LivePhysRegs.h | 74 void addReg(unsigned Reg) { in addReg()
84 void removeReg(unsigned Reg) { in removeReg()
102 bool contains(unsigned Reg) const { return LiveRegs.count(Reg); } in contains()
|
| D | LiveIntervalAnalysis.h | 110 LiveInterval &getInterval(unsigned Reg) { in getInterval()
117 const LiveInterval &getInterval(unsigned Reg) const { in getInterval()
121 bool hasInterval(unsigned Reg) const { in hasInterval()
126 LiveInterval &createEmptyInterval(unsigned Reg) { in createEmptyInterval()
133 LiveInterval &createAndComputeVirtRegInterval(unsigned Reg) { in createAndComputeVirtRegInterval()
140 void removeInterval(unsigned Reg) { in removeInterval()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.h | 34 static inline bool isARMArea1Register(unsigned Reg, bool isIOS) { in isARMArea1Register()
49 static inline bool isARMArea2Register(unsigned Reg, bool isIOS) { in isARMArea2Register()
60 static inline bool isARMArea3Register(unsigned Reg, bool isIOS) { in isARMArea3Register()
71 static inline bool isCalleeSavedRegister(unsigned Reg, in isCalleeSavedRegister()
|
| D | ARMCallingConv.h | 34 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS() local
49 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS() local
79 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList); in f64AssignAAPCS() local
129 unsigned Reg = State.AllocateReg(HiRegList, LoRegList); in f64RetAssign() local
266 for (auto Reg : RegList) in CC_ARM_AAPCS_Custom_Aggregate() local
|
| /external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| D | SystemZMCTargetDesc.h | 62 inline unsigned getRegAsGR64(unsigned Reg) { in getRegAsGR64()
67 inline unsigned getRegAsGR32(unsigned Reg) { in getRegAsGR32()
72 inline unsigned getRegAsGRH32(unsigned Reg) { in getRegAsGRH32()
77 inline unsigned getRegAsVR128(unsigned Reg) { in getRegAsVR128()
|
| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 1012 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); in DecodeGPR64RegisterClass() local
1023 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); in DecodeGPRMM16RegisterClass() local
1034 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); in DecodeGPRMM16ZeroRegisterClass() local
1045 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); in DecodeGPRMM16MovePRegisterClass() local
1056 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); in DecodeGPR32RegisterClass() local
1085 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); in DecodeFGR64RegisterClass() local
1097 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); in DecodeFGR32RegisterClass() local
1108 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); in DecodeCCRRegisterClass() local
1119 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); in DecodeFCCRegisterClass() local
1130 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); in DecodeFGRCCRegisterClass() local
[all …]
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZFrameLowering.cpp | 100 unsigned Reg = CSRegs[I]; in determineCalleeSaves() local
144 unsigned Reg = CSI[I].getReg(); in spillCalleeSavedRegisters() local
165 unsigned Reg = SystemZ::ArgGPRs[FirstGPR]; in spillCalleeSavedRegisters() local
190 unsigned Reg = CSI[I].getReg(); in spillCalleeSavedRegisters() local
203 unsigned Reg = CSI[I].getReg(); in spillCalleeSavedRegisters() local
230 unsigned Reg = CSI[I].getReg(); in restoreCalleeSavedRegisters() local
260 unsigned Reg = CSI[I].getReg(); in restoreCalleeSavedRegisters() local
289 unsigned Reg, int64_t NumBytes, in emitIncrement()
343 unsigned Reg = Save.getReg(); in emitPrologue() local
390 unsigned Reg = Save.getReg(); in emitPrologue() local
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsOptimizePICCall.cpp | 118 static MVT::SimpleValueType getRegTy(unsigned Reg, MachineFunction &MF) { in getRegTy()
148 unsigned Reg = Ty == MVT::i32 ? Mips::GP : Mips::GP_64; in eraseGPOpnd() local
214 unsigned Reg; in visitNode() local
246 bool OptimizePICCall::isCallViaRegister(MachineInstr &MI, unsigned &Reg, in isCallViaRegister()
288 unsigned Reg = ScopedHT.lookup(Entry).second; in getReg() local
293 void OptimizePICCall::incCntAndSetReg(ValueType Entry, unsigned Reg) { in incCntAndSetReg()
|
| D | MipsMachineFunction.h | 43 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } in setSRetReturnReg()
66 int getEhDataRegFI(unsigned Reg) const { return EhDataRegFI[Reg]; } in getEhDataRegFI()
78 int getISRRegFI(unsigned Reg) const { return ISRDataRegFI[Reg]; } in getISRRegFI()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 73 inline static unsigned getHexagonRegisterPair(unsigned Reg, in getHexagonRegisterPair()
278 MCOperand &Reg = MappedInst.getOperand(0); in HexagonProcessInstruction() local
297 MCOperand &Reg = MappedInst.getOperand(0); in HexagonProcessInstruction() local
322 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction() local
333 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction() local
345 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction() local
357 unsigned Reg = RI->getEncodingValue(Rs.getReg()); in HexagonProcessInstruction() local
539 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction() local
|
| D | BitTracker.h | 79 BitRef(unsigned R = 0, uint16_t P = 0) : Reg(R), Pos(P) {} in Reg() function
84 unsigned Reg; member
93 : Reg(R), Sub(S) {} in Reg() function
96 unsigned Reg, Sub; member
298 inline bool BitTracker::has(unsigned Reg) const { in has()
304 BitTracker::lookup(unsigned Reg) const { in lookup()
312 BitTracker::RegisterCell::self(unsigned Reg, uint16_t Width) { in self()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 95 bool contains(unsigned Reg) const { in contains()
282 static bool isStackSlot(unsigned Reg) { in isStackSlot()
287 static int stackSlot2Index(unsigned Reg) { in stackSlot2Index()
300 static bool isPhysicalRegister(unsigned Reg) { in isPhysicalRegister()
307 static bool isVirtualRegister(unsigned Reg) { in isVirtualRegister()
314 static unsigned virtReg2Index(unsigned Reg) { in virtReg2Index()
414 bool hasRegUnit(unsigned Reg, unsigned RegUnit) const { in hasRegUnit()
480 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg()
734 virtual void updateRegAllocHint(unsigned Reg, unsigned NewReg, in updateRegAllocHint()
785 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, in hasReservedSpillSlot()
[all …]
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.cpp | 64 unsigned Reg, unsigned FrameReg, int Offset ) { in InsertFPImmInst()
95 unsigned Reg, unsigned FrameReg, in InsertFPConstInst()
131 unsigned Reg, int Offset) { in InsertSPImmInst()
164 unsigned Reg, int Offset, RegScavenger *RS ) { in InsertSPConstInst()
306 unsigned Reg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local
|
| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg()
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { in getSubReg()
38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const { in getSubRegIndex()
|