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Searched defs:StoreToOffset (Results 1 – 12 of 12) sorted by relevance

/art/compiler/utils/mips64/
Dassembler_mips64_test.cc1383 TEST_F(AssemblerMIPS64Test, StoreToOffset) { in TEST_F() argument
1384 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A0, 0); in TEST_F() local
1385 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 0); in TEST_F() local
1386 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 1); in TEST_F() local
1387 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 256); in TEST_F() local
1388 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 1000); in TEST_F() local
1389 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 0x7FFF); in TEST_F() local
1390 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 0x8000); in TEST_F() local
1391 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 0x8001); in TEST_F() local
1392 __ StoreToOffset(mips64::kStoreByte, mips64::A0, mips64::A1, 0x10000); in TEST_F() local
[all …]
Dassembler_mips64.cc1906 void Mips64Assembler::StoreToOffset(StoreOperandType type, GpuRegister reg, GpuRegister base, in StoreToOffset() function in art::mips64::Mips64Assembler
/art/compiler/utils/mips/
Dassembler_mips_test.cc1008 TEST_F(AssemblerMIPSTest, StoreToOffset) { in TEST_F() argument
1009 __ StoreToOffset(mips::kStoreByte, mips::A0, mips::A0, 0); in TEST_F() local
1010 __ StoreToOffset(mips::kStoreByte, mips::A0, mips::A1, 0); in TEST_F() local
1011 __ StoreToOffset(mips::kStoreByte, mips::A0, mips::A1, 256); in TEST_F() local
1012 __ StoreToOffset(mips::kStoreByte, mips::A0, mips::A1, 1000); in TEST_F() local
1013 __ StoreToOffset(mips::kStoreByte, mips::A0, mips::A1, 0x8000); in TEST_F() local
1014 __ StoreToOffset(mips::kStoreByte, mips::A0, mips::A1, 0x10000); in TEST_F() local
1015 __ StoreToOffset(mips::kStoreByte, mips::A0, mips::A1, 0x12345678); in TEST_F() local
1016 __ StoreToOffset(mips::kStoreByte, mips::A0, mips::A1, -256); in TEST_F() local
1017 __ StoreToOffset(mips::kStoreByte, mips::A0, mips::A1, 0xFFFF8000); in TEST_F() local
[all …]
Dassembler_mips.cc2366 void MipsAssembler::StoreToOffset(StoreOperandType type, Register reg, Register base, in StoreToOffset() function in art::mips::MipsAssembler
/art/compiler/utils/
Dassembler_thumb_test.cc868 TEST_F(Thumb2AssemblerTest, StoreToOffset) { in TEST_F() argument
869 __ StoreToOffset(kStoreWord, R2, R4, 12); in TEST_F() local
870 __ StoreToOffset(kStoreWord, R2, R4, 0xfff); in TEST_F() local
871 __ StoreToOffset(kStoreWord, R2, R4, 0x1000); in TEST_F() local
872 __ StoreToOffset(kStoreWord, R2, R4, 0x1000a4); in TEST_F() local
873 __ StoreToOffset(kStoreWord, R2, R4, 0x101000); in TEST_F() local
874 __ StoreToOffset(kStoreWord, R4, R4, 0x101000); in TEST_F() local
875 __ StoreToOffset(kStoreHalfword, R2, R4, 12); in TEST_F() local
876 __ StoreToOffset(kStoreHalfword, R2, R4, 0xfff); in TEST_F() local
877 __ StoreToOffset(kStoreHalfword, R2, R4, 0x1000); in TEST_F() local
[all …]
/art/compiler/utils/arm/
Dassembler_thumb2_test.cc287 __ StoreToOffset(type, arm::R0, arm::SP, offset); in TEST_F() local
288 __ StoreToOffset(type, arm::IP, arm::SP, offset); in TEST_F() local
289 __ StoreToOffset(type, arm::IP, arm::R5, offset); in TEST_F() local
303 __ StoreToOffset(type, arm::R0, arm::SP, offset); in TEST_F() local
304 __ StoreToOffset(type, arm::IP, arm::SP, offset); in TEST_F() local
305 __ StoreToOffset(type, arm::IP, arm::R5, offset); in TEST_F() local
328 __ StoreToOffset(type, arm::R0, arm::SP, offset); in TEST_F() local
337 __ StoreToOffset(type, arm::R11, arm::SP, offset); in TEST_F() local
338 __ StoreToOffset(type, arm::R11, arm::R5, offset); in TEST_F() local
352 __ StoreToOffset(type, arm::R0, arm::SP, offset); in TEST_F() local
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Dassembler_arm32.cc1544 void Arm32Assembler::StoreToOffset(StoreOperandType type, in StoreToOffset() function in art::arm::Arm32Assembler
Dassembler_thumb2.cc3733 void Thumb2Assembler::StoreToOffset(StoreOperandType type, in StoreToOffset() function in art::arm::Thumb2Assembler
/art/compiler/optimizing/
Dcode_generator_arm.cc743 __ StoreToOffset(kStoreWord, static_cast<Register>(reg_id), SP, stack_index); in SaveCoreRegister() local
926 __ StoreToOffset(kStoreWord, kMethodRegisterArgument, SP, 0); in GenerateFrameEntry() local
1090 __ StoreToOffset(kStoreWord, source.AsRegister<Register>(), SP, destination.GetStackIndex()); in Move32() local
1096 __ StoreToOffset(kStoreWord, IP, SP, destination.GetStackIndex()); in Move32() local
1144 __ StoreToOffset(kStoreWord, R1, SP, destination.GetStackIndex()); in Move64() local
1145 __ StoreToOffset(kStoreWord, R2, SP, destination.GetHighStackIndex(kArmWordSize)); in Move64() local
1147 __ StoreToOffset(kStoreWordPair, source.AsRegisterPairLow<Register>(), in Move64() local
3831 __ StoreToOffset(kStoreByte, value.AsRegister<Register>(), base, offset); in HandleFieldSet() local
3837 __ StoreToOffset(kStoreHalfword, value.AsRegister<Register>(), base, offset); in HandleFieldSet() local
3851 __ StoreToOffset(kStoreWord, temp, base, offset); in HandleFieldSet() local
[all …]
Dcode_generator_mips64.cc503 __ StoreToOffset(store_type, in Exchange() local
507 __ StoreToOffset(store_type, TMP, SP, index1 + stack_offset); in Exchange() local
749 __ StoreToOffset(store_type, in MoveLocation() local
778 __ StoreToOffset(store_type, gpr, SP, destination.GetStackIndex()); in MoveLocation() local
785 __ StoreToOffset(kStoreWord, TMP, SP, destination.GetStackIndex()); in MoveLocation() local
788 __ StoreToOffset(kStoreDoubleword, TMP, SP, destination.GetStackIndex()); in MoveLocation() local
848 __ StoreToOffset(store_type, reg_loc.AsRegister<GpuRegister>(), SP, mem_loc.GetStackIndex()); in SwapLocations() local
930 __ StoreToOffset(kStoreDoubleword, GpuRegister(reg_id), SP, stack_index); in SaveCoreRegister() local
1474 __ StoreToOffset(kStoreByte, value, obj, offset); in VisitArraySet() local
1477 __ StoreToOffset(kStoreByte, value, TMP, data_offset); in VisitArraySet() local
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Dcode_generator_mips.cc612 __ StoreToOffset(kStoreWord, TMP, SP, offset); in EmitSwap() local
625 __ StoreToOffset(kStoreWord, TMP, SP, offset_l); in EmitSwap() local
628 __ StoreToOffset(kStoreWord, TMP, SP, offset_h); in EmitSwap() local
658 __ StoreToOffset(kStoreWord, in Exchange() local
662 __ StoreToOffset(kStoreWord, TMP, SP, index1 + stack_offset); in Exchange() local
849 __ StoreToOffset(kStoreWord, source.AsRegister<Register>(), SP, destination.GetStackIndex()); in Move32() local
855 __ StoreToOffset(kStoreWord, TMP, SP, destination.GetStackIndex()); in Move32() local
898 __ StoreToOffset(kStoreDoubleword, source.AsRegisterPairLow<Register>(), SP, off); in Move64() local
904 __ StoreToOffset(kStoreWord, TMP, SP, off); in Move64() local
906 __ StoreToOffset(kStoreWord, TMP, SP, off + 4); in Move64() local
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/art/compiler/utils/arm64/
Dassembler_arm64.cc114 void Arm64Assembler::StoreToOffset(XRegister source, XRegister base, int32_t offset) { in StoreToOffset() function in art::arm64::Arm64Assembler