Home
last modified time | relevance | path

Searched +full:0 +full:v (Results 1 – 25 of 1415) sorted by relevance

12345678910>>...57

/external/libxml2/result/
Datt48 <val o="0" v="53"/>
9 <val o="e08" v="53"/>
10 <val o="1c32" v="53"/>
11 <val o="2a3c" v="53"/>
12 <val o="3835" v="53"/>
13 <val o="4645" v="53"/>
14 <val o="5455" v="53"/>
15 <val o="6265" v="53"/>
16 <val o="7075" v="53"/>
17 <val o="7e85" v="53"/>
[all …]
Datt4.sax19 SAX.startElement(val, o='0', v='53')
23 SAX.startElement(val, o='e08', v='53')
27 SAX.startElement(val, o='1c32', v='53')
31 SAX.startElement(val, o='2a3c', v='53')
35 SAX.startElement(val, o='3835', v='53')
39 SAX.startElement(val, o='4645', v='53')
43 SAX.startElement(val, o='5455', v='53')
47 SAX.startElement(val, o='6265', v='53')
51 SAX.startElement(val, o='7075', v='53')
55 SAX.startElement(val, o='7e85', v='53')
[all …]
/external/libxml2/result/noent/
Datt48 <val o="0" v="53"/>
9 <val o="e08" v="53"/>
10 <val o="1c32" v="53"/>
11 <val o="2a3c" v="53"/>
12 <val o="3835" v="53"/>
13 <val o="4645" v="53"/>
14 <val o="5455" v="53"/>
15 <val o="6265" v="53"/>
16 <val o="7075" v="53"/>
17 <val o="7e85" v="53"/>
[all …]
/external/libxml2/test/
Datt48 <val o="0" v="53"/>
9 <val o="e08" v="53"/>
10 <val o="1c32" v="53"/>
11 <val o="2a3c" v="53"/>
12 <val o="3835" v="53"/>
13 <val o="4645" v="53"/>
14 <val o="5455" v="53"/>
15 <val o="6265" v="53"/>
16 <val o="7075" v="53"/>
17 <val o="7e85" v="53"/>
[all …]
/external/clang/test/CodeGen/
Daarch64-neon-2velem.c8 int16x4_t test_vmla_lane_s16(int16x4_t a, int16x4_t b, int16x4_t v) { in test_vmla_lane_s16() argument
10 return vmla_lane_s16(a, b, v, 3); in test_vmla_lane_s16()
11 // CHECK: mla {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3] in test_vmla_lane_s16()
14 int16x8_t test_vmlaq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t v) { in test_vmlaq_lane_s16() argument
16 return vmlaq_lane_s16(a, b, v, 3); in test_vmlaq_lane_s16()
17 // CHECK: mla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[3] in test_vmlaq_lane_s16()
20 int32x2_t test_vmla_lane_s32(int32x2_t a, int32x2_t b, int32x2_t v) { in test_vmla_lane_s32() argument
22 return vmla_lane_s32(a, b, v, 1); in test_vmla_lane_s32()
23 // CHECK: mla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1] in test_vmla_lane_s32()
26 int32x4_t test_vmlaq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t v) { in test_vmlaq_lane_s32() argument
[all …]
Daarch64-neon-fma.c11 // CHECK: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0] in test_vmla_n_f32()
12 // CHECK: fadd {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s in test_vmla_n_f32()
13 // CHECK-FMA: dup {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0] in test_vmla_n_f32()
14 // CHECK-FMA: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s in test_vmla_n_f32()
20 // CHECK: fmul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0] in test_vmlaq_n_f32()
21 // CHECK: fadd {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s in test_vmlaq_n_f32()
22 // CHECK-FMA: dup {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0] in test_vmlaq_n_f32()
23 // CHECK-FMA: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s in test_vmlaq_n_f32()
29 // CHECK: fmul {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0] in test_vmlaq_n_f64()
30 // CHECK: fadd {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d in test_vmlaq_n_f64()
[all …]
Daarch64-neon-tbl.c12 // CHECK: tbl {{v[0-9]+}}.8b, {{{ ?v[0-9]+.16b ?}}}, {{v[0-9]+}}.8b in test_vtbl1_s8()
18 // CHECK: tbl {{v[0-9]+}}.8b, {{{ ?v[0-9]+.16b ?}}}, {{v[0-9]+}}.8b in test_vqtbl1_s8()
24 // CHECK: tbl {{v[0-9]+}}.8b, {{{ ?v[0-9]+.16b ?}}}, {{v[0-9]+}}.8b in test_vtbl2_s8()
30 // CHECK: tbl {{v[0-9]+}}.8b, {{{ ?v[0-9]+.16b, v[0-9]+.16b ?}}}, {{v[0-9]+}}.8b in test_vqtbl2_s8()
36 // CHECK: tbl {{v[0-9]+}}.8b, {{{ ?v[0-9]+.16b, v[0-9]+.16b ?}}}, {{v[0-9]+}}.8b in test_vtbl3_s8()
42 // CHECK: tbl {{v[0-9]+}}.8b, {{{ ?v[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b ?}}}, {{v[0-9]+}}.8b in test_vqtbl3_s8()
48 // CHECK: tbl {{v[0-9]+}}.8b, {{{ ?v[0-9]+.16b, v[0-9]+.16b ?}}}, {{v[0-9]+}}.8b in test_vtbl4_s8()
54 …// CHECK: tbl {{v[0-9]+}}.8b, {{{ ?v[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b ?}}}, {{v[0-… in test_vqtbl4_s8()
60 // CHECK: tbl {{v[0-9]+}}.16b, {{{ ?v[0-9]+.16b ?}}}, {{v[0-9]+}}.16b in test_vqtbl1q_s8()
66 // CHECK: tbl {{v[0-9]+}}.16b, {{{ ?v[0-9]+.16b, v[0-9]+.16b ?}}}, {{v[0-9]+}}.16b in test_vqtbl2q_s8()
[all …]
Daarch64-neon-misc.c10 // CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}}
16 // CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}}
22 // CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}}
28 // CHECK: cmeq {{d[0-9]+}}, {{d[0-9]+}}, #{{0x0|0}}
34 // CHECK: cmeq {{d[0-9]+}}, {{d[0-9]+}}, #{{0x0|0}}
40 // CHECK: cmeq {{d[0-9]+}}, {{d[0-9]+}}, #{{0x0|0}}
46 // CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}}
52 // CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}}
58 // CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}}
64 // CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}}
[all …]
Daarch64-neon-3v.c11 // CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b in test_vand_s8()
17 // CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b in test_vandq_s8()
23 // CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b in test_vand_s16()
29 // CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b in test_vandq_s16()
35 // CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b in test_vand_s32()
41 // CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b in test_vandq_s32()
47 // CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b in test_vand_s64()
53 // CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b in test_vandq_s64()
59 // CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b in test_vand_u8()
65 // CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b in test_vandq_u8()
[all …]
Daarch64-neon-perm.c11 // CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b in test_vuzp1_s8()
17 // CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b in test_vuzp1q_s8()
23 // CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h in test_vuzp1_s16()
29 // CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h in test_vuzp1q_s16()
35 // CHECK: {{ins v[0-9]+.s\[1\], v[0-9]+.s\[0\]|zip1 v0.2s, v0.2s, v1.2s}} in test_vuzp1_s32()
41 // CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s in test_vuzp1q_s32()
47 // CHECK: {{ins v[0-9]+.d\[1\], v[0-9]+.d\[0\]|zip1 v0.2d, v0.2d, v1.2d}} in test_vuzp1q_s64()
53 // CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b in test_vuzp1_u8()
59 // CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b in test_vuzp1q_u8()
65 // CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h in test_vuzp1_u16()
[all …]
Daarch64-neon-ldst-one.c10 // CHECK: ld1r {{{ *v[0-9]+.16b *}}}, [{{x[0-9]+|sp}}] in test_vld1q_dup_u8()
16 // CHECK: ld1r {{{ *v[0-9]+.8h *}}}, [{{x[0-9]+|sp}}] in test_vld1q_dup_u16()
22 // CHECK: ld1r {{{ *v[0-9]+.4s *}}}, [{{x[0-9]+|sp}}] in test_vld1q_dup_u32()
28 // CHECK: ld1r {{{ *v[0-9]+.2d *}}}, [{{x[0-9]+|sp}}] in test_vld1q_dup_u64()
34 // CHECK: ld1r {{{ *v[0-9]+.16b *}}}, [{{x[0-9]+|sp}}] in test_vld1q_dup_s8()
40 // CHECK: ld1r {{{ *v[0-9]+.8h *}}}, [{{x[0-9]+|sp}}] in test_vld1q_dup_s16()
46 // CHECK: ld1r {{{ *v[0-9]+.4s *}}}, [{{x[0-9]+|sp}}] in test_vld1q_dup_s32()
52 // CHECK: ld1r {{{ *v[0-9]+.2d *}}}, [{{x[0-9]+|sp}}] in test_vld1q_dup_s64()
58 // CHECK: ld1r {{{ *v[0-9]+.8h *}}}, [{{x[0-9]+|sp}}] in test_vld1q_dup_f16()
64 // CHECK: ld1r {{{ *v[0-9]+.4s *}}}, [{{x[0-9]+|sp}}] in test_vld1q_dup_f32()
[all …]
Daarch64-neon-intrinsics.c12 // CHECK: add {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b in test_vadd_s8()
18 // CHECK: add {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h in test_vadd_s16()
24 // CHECK: add {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s in test_vadd_s32()
30 // CHECK: add {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} in test_vadd_s64()
36 // CHECK: fadd {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s in test_vadd_f32()
42 // CHECK: add {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b in test_vadd_u8()
48 // CHECK: add {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h in test_vadd_u16()
54 // CHECK: add {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s in test_vadd_u32()
60 // CHECK: add {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} in test_vadd_u64()
66 // CHECK: add {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b in test_vaddq_s8()
[all …]
/external/v8/src/wasm/
Dwasm-opcodes.h17 kLocalVoid = 0,
26 kMemI8 = 0,
53 kNone = 0, // non-atomic
60 enum Alignment { kAligned = 0, kUnaligned = 1 };
71 #define FOREACH_CONTROL_OPCODE(V) \ argument
72 V(Nop, 0x00, _) \
73 V(Block, 0x01, _) \
74 V(Loop, 0x02, _) \
75 V(If, 0x03, _) \
76 V(IfElse, 0x04, _) \
[all …]
/external/valgrind/none/tests/arm/
Dv6intThumb.stdout.exp1 CMP-16 0x10a
2 cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
3 cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
4 cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
5 cmp r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
6 cmp r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
7 cmp r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
8 cmp r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
9 cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
10 cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
[all …]
/external/llvm/test/MC/AMDGPU/
Dflat.s15 flat_load_dword v1, v[3:4]
17 // CIVI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x00,0x01]
19 flat_load_dword v1, v[3:4] glc
21 // CIVI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x00,0x01]
23 flat_load_dword v1, v[3:4] glc slc
25 // CIVI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x00,0x01]
27 flat_load_dword v1, v[3:4] glc tfe
29 // CIVI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x80,0x01]
31 flat_load_dword v1, v[3:4] glc slc tfe
33 // CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x0…
[all …]
Dds.s9 // CHECK: ds_add_u32 v2, v4 offset:16 ; encoding: [0x10,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
16 // CHECK: ds_write2_b32 v2, v4, v6 offset0:4 ; encoding: [0x04,0x00,0x38,0xd8,0x02,0x04,0x06,0x00]
19 … ds_write2_b32 v2, v4, v6 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x38,0xd8,0x02,0x04,0x06,0x00]
22 // CHECK: ds_write2_b32 v2, v4, v6 offset1:8 ; encoding: [0x00,0x08,0x38,0xd8,0x02,0x04,0x06,0x00]
24 ds_read2_b32 v[8:9], v2 offset0:4
25 // CHECK: ds_read2_b32 v[8:9], v2 offset0:4 ; encoding: [0x04,0x00,0xdc,0xd8,0x02,0x00,0x00,0x08]
27 ds_read2_b32 v[8:9], v2 offset0:4 offset1:8
28 // CHECK: ds_read2_b32 v[8:9], v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0xdc,0xd8,0x02,0x00,0x…
30 ds_read2_b32 v[8:9], v2 offset1:8
31 // CHECK: ds_read2_b32 v[8:9], v2 offset1:8 ; encoding: [0x00,0x08,0xdc,0xd8,0x02,0x00,0x00,0x08]
[all …]
/external/opencv3/3rdparty/libjpeg/
Djaricom.c29 #define V(i,a,b,c,d) (((INT32)a << 16) | ((INT32)c << 8) | ((INT32)d << 7) | b) macro
35 V( 0, 0x5a1d, 1, 1, 1 ),
36 V( 1, 0x2586, 14, 2, 0 ),
37 V( 2, 0x1114, 16, 3, 0 ),
38 V( 3, 0x080b, 18, 4, 0 ),
39 V( 4, 0x03d8, 20, 5, 0 ),
40 V( 5, 0x01da, 23, 6, 0 ),
41 V( 6, 0x00e5, 25, 7, 0 ),
42 V( 7, 0x006f, 28, 8, 0 ),
43 V( 8, 0x0036, 30, 9, 0 ),
[all …]
/external/libjpeg-turbo/
Djaricom.c29 #define V(i,a,b,c,d) (((INT32)a << 16) | ((INT32)c << 8) | ((INT32)d << 7) | b) macro
35 V( 0, 0x5a1d, 1, 1, 1 ),
36 V( 1, 0x2586, 14, 2, 0 ),
37 V( 2, 0x1114, 16, 3, 0 ),
38 V( 3, 0x080b, 18, 4, 0 ),
39 V( 4, 0x03d8, 20, 5, 0 ),
40 V( 5, 0x01da, 23, 6, 0 ),
41 V( 6, 0x00e5, 25, 7, 0 ),
42 V( 7, 0x006f, 28, 8, 0 ),
43 V( 8, 0x0036, 30, 9, 0 ),
[all …]
/external/autotest/client/site_tests/graphics_PiglitBVT/test_scripts/other/
Dgraphics_PiglitBVT_1.sh5 failures=0
9 export DISPLAY=:0
22 if [ $? == 0 ] ; then
33 run_test "asmparsertest/ARBfp1.0/abs-01.txt" 0.0 "bin/asmparsertest ARBfp1.0 tests/asmparsertest/sh…
34 run_test "asmparsertest/ARBfp1.0/abs-02.txt" 0.0 "bin/asmparsertest ARBfp1.0 tests/asmparsertest/sh…
35 run_test "asmparsertest/ARBfp1.0/cos-01.txt" 0.0 "bin/asmparsertest ARBfp1.0 tests/asmparsertest/sh…
36 run_test "asmparsertest/ARBfp1.0/cos-02.txt" 0.0 "bin/asmparsertest ARBfp1.0 tests/asmparsertest/sh…
37 run_test "asmparsertest/ARBfp1.0/cos-03.txt" 0.0 "bin/asmparsertest ARBfp1.0 tests/asmparsertest/sh…
38 run_test "asmparsertest/ARBfp1.0/cos-04.txt" 0.0 "bin/asmparsertest ARBfp1.0 tests/asmparsertest/sh…
39 run_test "asmparsertest/ARBfp1.0/ddx-01.txt" 0.0 "bin/asmparsertest ARBfp1.0 tests/asmparsertest/sh…
[all …]
/external/llvm/test/CodeGen/AArch64/
Daarch64-be-bv.ll7 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
8 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #0x1
9 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
10 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
12 %rv = add <8 x i16> %in, <i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0>
13 %el = extractelement <8 x i16> %rv, i32 0
19 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
20 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #0x1, lsl #8
21 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
22 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
[all …]
Darm64-neon-2velem.ll45 define <4 x i16> @test_vmla_lane_s16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %v) {
47 ; CHECK: mla {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]
50 %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
56 define <8 x i16> @test_vmlaq_lane_s16(<8 x i16> %a, <8 x i16> %b, <4 x i16> %v) {
58 ; CHECK: mla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[3]
61 …%shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32…
67 define <2 x i32> @test_vmla_lane_s32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %v) {
69 ; CHECK: mla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
72 %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
78 define <4 x i32> @test_vmlaq_lane_s32(<4 x i32> %a, <4 x i32> %b, <2 x i32> %v) {
[all …]
/external/mesa3d/src/mesa/main/
Dapi_arrayelt.c78 * in the range [0, 7]. Luckily these type tokens are sequentially
179 VertexAttrib1NbvNV(GLuint index, const GLbyte *v) in VertexAttrib1NbvNV() argument
181 CALL_VertexAttrib1fNV(GET_DISPATCH(), (index, BYTE_TO_FLOAT(v[0]))); in VertexAttrib1NbvNV()
185 VertexAttrib1bvNV(GLuint index, const GLbyte *v) in VertexAttrib1bvNV() argument
187 CALL_VertexAttrib1fNV(GET_DISPATCH(), (index, (GLfloat)v[0])); in VertexAttrib1bvNV()
191 VertexAttrib2NbvNV(GLuint index, const GLbyte *v) in VertexAttrib2NbvNV() argument
193 CALL_VertexAttrib2fNV(GET_DISPATCH(), (index, BYTE_TO_FLOAT(v[0]), BYTE_TO_FLOAT(v[1]))); in VertexAttrib2NbvNV()
197 VertexAttrib2bvNV(GLuint index, const GLbyte *v) in VertexAttrib2bvNV() argument
199 CALL_VertexAttrib2fNV(GET_DISPATCH(), (index, (GLfloat)v[0], (GLfloat)v[1])); in VertexAttrib2bvNV()
203 VertexAttrib3NbvNV(GLuint index, const GLbyte *v) in VertexAttrib3NbvNV() argument
[all …]
/external/valgrind/none/tests/s390x/
Dspechelper-tmll.c7 asm volatile( " tmll %[v]," #i2 "\n\t" \
9 " mvi %[taken],0\n\t" \
10 " j 0f\n\t" \
12 "0: bcr 0,0 /* nop */\n\t" \
14 : [v] "d"(v1) \
23 unsigned long v; in tmll_mask_0() local
25 printf("Test #1 mask == 0, value == ~0 --> cc == 0\n"); in tmll_mask_0()
27 v = ~0ULL; in tmll_mask_0()
28 wrong = ok = 0; in tmll_mask_0()
30 if (branch(0, 0, v)) ++wrong; else ++ok; in tmll_mask_0()
[all …]
Dspechelper-tm.c7 asm volatile( " tm %[v]," #i2 "\n\t" \
9 " mvi %[taken],0\n\t" \
10 " j 0f\n\t" \
12 "0: bcr 0,0 /* nop */\n\t" \
14 : [v] "Q"(v1) \
23 unsigned char v; in tm_mask_0() local
25 printf("Test #1 mask == 0, value == ~0 --> cc == 0\n"); in tm_mask_0()
27 v = ~0; in tm_mask_0()
28 wrong = ok = 0; in tm_mask_0()
30 if (branch(0, 0, v)) ++wrong; else ++ok; in tm_mask_0()
[all …]
/external/v8/src/compiler/
Dmachine-operator.cc95 #define PURE_OP_LIST(V) \ argument
96 V(Word32And, Operator::kAssociative | Operator::kCommutative, 2, 0, 1) \
97 V(Word32Or, Operator::kAssociative | Operator::kCommutative, 2, 0, 1) \
98 V(Word32Xor, Operator::kAssociative | Operator::kCommutative, 2, 0, 1) \
99 V(Word32Shl, Operator::kNoProperties, 2, 0, 1) \
100 V(Word32Shr, Operator::kNoProperties, 2, 0, 1) \
101 V(Word32Sar, Operator::kNoProperties, 2, 0, 1) \
102 V(Word32Ror, Operator::kNoProperties, 2, 0, 1) \
103 V(Word32Equal, Operator::kCommutative, 2, 0, 1) \
104 V(Word32Clz, Operator::kNoProperties, 1, 0, 1) \
[all …]

12345678910>>...57