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Searched refs:PC (Results 1 – 25 of 28) sorted by relevance

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/art/runtime/interpreter/mterp/x86/
Dop_mul_long.S15 mov rPC, LOCAL0(%esp) # save Interpreter PC
27 mov LOCAL0(%esp), rPC # restore Interpreter PC
Dop_mul_long_2addr.S17 mov rPC, LOCAL0(%esp) # save Interpreter PC
32 mov LOCAL0(%esp), rPC # restore Interpreter PC
Dop_packed_switch.S14 leal (rPC,%ecx,2), %ecx # ecx <- PC + BBBBbbbb*2
Dop_fill_array_data.S4 leal (rPC,%ecx,2), %ecx # ecx <- PC + BBBBbbbb*2
/art/runtime/interpreter/mterp/x86_64/
Dop_packed_switch.S13 leaq (rPC,OUT_ARG0,2), OUT_ARG0 # rcx <- PC + BBBBbbbb*2
Dop_fill_array_data.S4 leaq (rPC,%rcx,2), OUT_ARG1 # OUT_ARG1 <- PC + BBBBbbbb*2
/art/runtime/interpreter/mterp/mips/
Dop_packed_switch.S19 EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2
40 EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2
Dop_fill_array_data.S9 EAS1(a1, rPC, a1) # a1 <- PC + BBBBbbbb*2 (array data off.)
/art/runtime/arch/arm/
Dregisters_arm.cc29 if (rhs >= R0 && rhs <= PC) { in operator <<()
Dcontext_arm.cc32 gprs_[PC] = &pc_; in Reset()
36 pc_ = ArmContext::kBadGprBase + PC; in Reset()
Dregisters_arm.h48 PC = 15, enumerator
Dcontext_arm.h45 SetGPR(PC, new_pc); in SetPC()
/art/runtime/interpreter/mterp/arm/
Dop_packed_switch.S17 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2
Dop_fill_array_data.S8 add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.)
/art/runtime/interpreter/mterp/mips64/
Dop_fill_array_data.S9 dlsa a1, a1, rPC, 1 # a1 <- PC + BBBBbbbb*2 (array data off.)
Dop_packed_switch.S19 dlsa a0, a0, rPC, 1 # a0 <- PC + BBBBbbbb*2
/art/compiler/utils/arm/
Dassembler_arm32.cc112 CHECK_NE(rn, PC); // Reserve tst pc instruction for exception handler marker. in tst()
118 CHECK_NE(rn, PC); // Reserve teq pc instruction for exception handler marker. in teq()
559 EmitType01(AL, 1, TST, kCcSet, PC, R0, ShifterOperand(0)); in MarkExceptionHandler()
612 if (!ad.IsImmediate() && ad.GetRegisterOffset() == PC) { in EmitMemOp()
725 CHECK_NE(rd, PC); in clz()
726 CHECK_NE(rm, PC); in clz()
772 CHECK_NE(rd, PC); in EmitReverseBytes()
773 CHECK_NE(rm, PC); in EmitReverseBytes()
786 CHECK_NE(rd, PC); in rbit()
787 CHECK_NE(rm, PC); in rbit()
[all …]
Dassembler_thumb2.cc415 return LdrRtRnImm12Encoding(rt, PC, offset); in LdrLitEncoding32()
591 CHECK_NE(rn, PC); // Reserve tst pc instruction for exception handler marker. in tst()
597 CHECK_NE(rn, PC); // Reserve teq pc instruction for exception handler marker. in teq()
1154 EmitDataProcessing(AL, TST, kCcSet, PC, R0, ShifterOperand(0)); in MarkExceptionHandler()
1354 case TST: thumb_opcode = 0U /* 0b0000 */; DCHECK(set_cc == kCcSet); rd = PC; break; in Emit32BitDataProcessing()
1355 case TEQ: thumb_opcode = 4U /* 0b0100 */; DCHECK(set_cc == kCcSet); rd = PC; break; in Emit32BitDataProcessing()
1356 case CMP: thumb_opcode = 13U /* 0b1101 */; DCHECK(set_cc == kCcSet); rd = PC; break; in Emit32BitDataProcessing()
1357 case CMN: thumb_opcode = 8U /* 0b1000 */; DCHECK(set_cc == kCcSet); rd = PC; break; in Emit32BitDataProcessing()
1359 case MOV: thumb_opcode = 2U /* 0b0010 */; rn = PC; break; in Emit32BitDataProcessing()
1361 case MVN: thumb_opcode = 3U /* 0b0011 */; rn = PC; break; in Emit32BitDataProcessing()
[all …]
Dassembler_arm.h278 CHECK_NE(rm, PC); in rn_()
284 CHECK_NE(rm, PC); in rn_()
289 rn_(PC), rm_(R0), offset_(offset), in Address()
Dassembler_arm.cc41 if (rhs >= R0 && rhs <= PC) { in operator <<()
450 RegList core_spill_mask = 1 << PC; in RemoveFrame()
/art/compiler/trampolines/
Dtrampoline_compiler.cc58 __ LoadFromOffset(kLoadWord, PC, R0, offset.Int32Value()); in CreateTrampoline()
62 __ LoadFromOffset(kLoadWord, PC, IP, offset.Int32Value()); in CreateTrampoline()
65 __ LoadFromOffset(kLoadWord, PC, R9, offset.Int32Value()); in CreateTrampoline()
/art/disassembler/
Ddisassembler_arm.cc1383 if (Rt.r == PC && is_load && !is_word) { in DumpThumb32()
1389 } else if (Rn.r == PC || U != 0u) { in DumpThumb32()
1392 if (Rn.r == PC && is_half) { in DumpThumb32()
1410 bool unpred = (Rt.r == SP && !is_word) || (Rt.r == PC && !is_load); in DumpThumb32()
1411 if (Rn.r == PC && !is_load) { in DumpThumb32()
1414 } else if (Rn.r == PC || U != 0u) { in DumpThumb32()
1421 } else if (Rn.r == PC) { in DumpThumb32()
1436 unpred = unpred || (Rm.rm.r == SP) || (Rm.rm.r == PC); in DumpThumb32()
/art/compiler/linker/arm/
Drelative_patcher_thumb2.cc86 arm::kLoadWord, arm::PC, arm::R0, in CompileThunkCode()
/art/runtime/interpreter/mterp/out/
Dmterp_x86.S1054 leal (rPC,%ecx,2), %ecx # ecx <- PC + BBBBbbbb*2
1146 leal (rPC,%ecx,2), %ecx # ecx <- PC + BBBBbbbb*2
1172 leal (rPC,%ecx,2), %ecx # ecx <- PC + BBBBbbbb*2
4270 mov rPC, LOCAL0(%esp) # save Interpreter PC
4282 mov LOCAL0(%esp), rPC # restore Interpreter PC
4999 mov rPC, LOCAL0(%esp) # save Interpreter PC
5014 mov LOCAL0(%esp), rPC # restore Interpreter PC
/art/compiler/optimizing/
Dcode_generator_arm.cc834 blocked_core_registers_[PC] = true; in SetupBlockedRegisters()
946 uint32_t pop_mask = (core_spill_mask_ & (~(1 << LR))) | 1 << PC; in GenerateFrameExit()
5238 __ add(out, out, ShifterOperand(PC)); in VisitLoadString()
6728 __ add(base_reg, base_reg, ShifterOperand(PC)); in VisitArmDexCacheArraysBase()

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