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/external/elfutils/tests/
Drun-allregs.sh32 0: %eax (eax), signed 32 bits
33 1: %ecx (ecx), signed 32 bits
34 2: %edx (edx), signed 32 bits
35 3: %ebx (ebx), signed 32 bits
36 4: %esp (esp), address 32 bits
37 5: %ebp (ebp), address 32 bits
38 6: %esi (esi), signed 32 bits
39 7: %edi (edi), signed 32 bits
40 8: %eip (eip), address 32 bits
41 9: %eflags (eflags), unsigned 32 bits
[all …]
/external/valgrind/memcheck/tests/vbit-test/
Dvbits.c55 case 1: return v.bits.u32; in get_bits64()
56 case 8: return v.bits.u8; in get_bits64()
57 case 16: return v.bits.u16; in get_bits64()
58 case 32: return v.bits.u32; in get_bits64()
59 case 64: return v.bits.u64; in get_bits64()
72 case 1: fprintf(fp, "%08x", v.bits.u32); break; in print_vbits()
73 case 8: fprintf(fp, "%02x", v.bits.u8); break; in print_vbits()
74 case 16: fprintf(fp, "%04x", v.bits.u16); break; in print_vbits()
75 case 32: fprintf(fp, "%08x", v.bits.u32); break; in print_vbits()
76 case 64: fprintf(fp, "%016"PRIx64, v.bits.u64); break; in print_vbits()
[all …]
/external/speex/libspeex/
Dbits.c48 EXPORT void speex_bits_init(SpeexBits *bits) in speex_bits_init() argument
50 bits->chars = (char*)speex_alloc(MAX_CHARS_PER_FRAME); in speex_bits_init()
51 if (!bits->chars) in speex_bits_init()
54 bits->buf_size = MAX_CHARS_PER_FRAME; in speex_bits_init()
56 bits->owner=1; in speex_bits_init()
58 speex_bits_reset(bits); in speex_bits_init()
61 EXPORT void speex_bits_init_buffer(SpeexBits *bits, void *buff, int buf_size) in speex_bits_init_buffer() argument
63 bits->chars = (char*)buff; in speex_bits_init_buffer()
64 bits->buf_size = buf_size; in speex_bits_init_buffer()
66 bits->owner=0; in speex_bits_init_buffer()
[all …]
/external/llvm/lib/Target/Mips/
DMicroMipsInstrFormats.td35 field bits<16> Inst;
36 field bits<16> SoftFail = 0;
37 bits<6> Opcode = 0x0;
45 bits<3> rd;
46 bits<3> rt;
47 bits<3> rs;
49 bits<16> Inst;
58 class ANDI_FM_MM16<bits<6> funct> {
59 bits<3> rd;
60 bits<3> rs;
[all …]
DMipsMSAInstrFormats.td30 class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
31 bits<5> ws;
32 bits<5> wd;
33 bits<3> m;
43 class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
44 bits<5> ws;
45 bits<5> wd;
46 bits<4> m;
56 class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
57 bits<5> ws;
[all …]
DMicroMips32r6InstrFormats.td26 bits<10> offset;
28 bits<16> Inst;
34 class BEQZC_BNEZC_FM_MM16R6<bits<6> op> : MicroMipsR6Inst16 {
35 bits<3> rs;
36 bits<7> offset;
38 bits<16> Inst;
45 class POOL16C_JALRC_FM_MM16R6<bits<5> op> {
46 bits<5> rs;
48 bits<16> Inst;
55 class POOL16C_JRCADDIUSP_FM_MM16R6<bits<5> op> {
[all …]
DMipsInstrFormats.td27 class Format<bits<4> val> {
28 bits<4> Value = val;
75 field bits<32> Inst;
82 bits<6> Opcode = 0;
84 // Top 6 bits are the 'opcode' field
97 bits<4> FormBits = Form.Value;
104 field bits<32> SoftFail = 0;
143 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
147 bits<5> rd;
148 bits<5> rs;
[all …]
DMips32r6InstrFormats.td45 class OPGROUP<bits<6> Val> {
46 bits<6> Value = Val;
66 class OPCODE2<bits<2> Val> {
67 bits<2> Value = Val;
73 class OPCODE3<bits<3> Val> {
74 bits<3> Value = Val;
78 class OPCODE5<bits<5> Val> {
79 bits<5> Value = Val;
97 class OPCODE6<bits<6> Val> {
98 bits<6> Value = Val;
[all …]
DMicroMipsDSPInstrFormats.td25 class POOL32A_3R_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
26 bits<5> rd;
27 bits<5> rs;
28 bits<5> rt;
37 class POOL32A_2R_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
38 bits<5> rt;
39 bits<5> rs;
48 class POOL32A_2RAC_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> {
49 bits<5> rt;
50 bits<5> rs;
[all …]
DMipsDSPInstrFormats.td36 class Field6<bits<6> val> {
37 bits<6> V = val;
62 class ADDU_QB_FMT<bits<5> op> : DSPInst {
63 bits<5> rd;
64 bits<5> rs;
65 bits<5> rt;
76 class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
77 bits<5> rd;
78 bits<5> rs;
90 class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
[all …]
DMips16InstrFormats.td59 field bits<16> Inst;
60 bits<5> Opcode = 0;
62 // Top 5 bits are the 'opcode' field
66 field bits<16> SoftFail = 0;
76 field bits<32> Inst;
79 field bits<32> SoftFail = 0;
103 class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,
107 bits<11> imm11;
118 class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
122 bits<3> rx;
[all …]
/external/llvm/lib/Target/AMDGPU/
DR600InstrFormats.td18 field bits<64> Inst;
22 bits<2> FlagOperandIdx = 0;
68 field bits<32> Word0;
70 bits<11> src0;
71 bits<1> src0_rel;
72 bits<11> src1;
73 bits<1> src1_rel;
74 bits<3> index_mode = 0;
75 bits<2> pred_sel;
76 bits<1> last;
[all …]
DVIInstrFormats.td14 class DSe_vi <bits<8> op> : Enc64 {
15 bits<8> vdst;
16 bits<1> gds;
17 bits<8> addr;
18 bits<8> data0;
19 bits<8> data1;
20 bits<8> offset0;
21 bits<8> offset1;
34 class MUBUFe_vi <bits<7> op> : Enc64 {
35 bits<12> offset;
[all …]
DSIInstrFormats.td17 field bits<1> VM_CNT = 0;
18 field bits<1> EXP_CNT = 0;
19 field bits<1> LGKM_CNT = 0;
21 field bits<1> SALU = 0;
22 field bits<1> VALU = 0;
24 field bits<1> SOP1 = 0;
25 field bits<1> SOP2 = 0;
26 field bits<1> SOPC = 0;
27 field bits<1> SOPK = 0;
28 field bits<1> SOPP = 0;
[all …]
/external/llvm/test/TableGen/
DBitsInit.td6 bits<2> opc = { 0, 1 };
7 bits<2> opc2 = { 1, 0 };
8 bits<1> opc3 = { 1 };
9 bits<2> a = { opc, opc2 }; // error!
10 bits<2> b = { opc{0}, opc2{0} };
11 bits<2> c = { opc{1}, opc2{1} };
12 bits<2> c = { opc3{0}, opc3 };
16 // CHECK: bits<2> opc = { 0, 1 };
17 // CHECK: bits<2> opc2 = { 1, 0 };
18 // CHECK: bits<1> opc3 = { 1 };
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstrFormats.td14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
16 field bits<32> Inst;
17 field bits<32> SoftFail = 0;
29 bits<1> PPC970_First = 0;
30 bits<1> PPC970_Single = 0;
31 bits<1> PPC970_Cracked = 0;
32 bits<3> PPC970_Unit = 0;
51 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
52 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
53 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
[all …]
/external/antlr/antlr-3.4/tool/src/main/java/org/antlr/misc/
DBitSet.java65 protected long bits[]; field in BitSet
74 bits = bits_; in BitSet()
81 bits = new long[((nbits - 1) >> LOG_BITS) + 1]; in BitSet()
90 if (n >= bits.length) { in add()
93 bits[n] |= bitMask(el); in add()
158 int min = Math.min(bits.length, a.bits.length); in andInPlace()
160 bits[i] &= a.bits[i]; in andInPlace()
163 for (int i = min; i < bits.length; i++) { in andInPlace()
164 bits[i] = 0; in andInPlace()
174 for (int i = bits.length - 1; i >= 0; i--) { in clear()
[all …]
/external/webrtc/webrtc/modules/audio_coding/codecs/g711/
Dg711.h58 static __inline__ int top_bit(unsigned int bits) { in top_bit() argument
64 : "a" (bits)); in top_bit()
71 static __inline__ int bottom_bit(unsigned int bits) { in bottom_bit() argument
77 : "a" (bits)); in bottom_bit()
81 static __inline__ int top_bit(unsigned int bits) {
87 : "a" (bits));
91 static __inline__ int bottom_bit(unsigned int bits) {
97 : "a" (bits));
101 static __inline int top_bit(unsigned int bits) {
104 if (bits == 0) {
[all …]
/external/antlr/antlr-3.4/runtime/Java/src/main/java/org/antlr/runtime/
DBitSet.java48 protected long bits[]; field in BitSet
57 bits = bits_; in BitSet()
73 bits = new long[((nbits - 1) >> LOG_BITS) + 1]; in BitSet()
119 if (n >= bits.length) { in add()
122 bits[n] |= bitMask(el); in add()
130 int newSize = Math.max(bits.length << 1, numWordsToHold(bit)); in growToInclude()
132 System.arraycopy(bits, 0, newbits, 0, bits.length); in growToInclude()
133 bits = newbits; in growToInclude()
141 if (a.bits.length > bits.length) { in orInPlace()
142 setSize(a.bits.length); in orInPlace()
[all …]
/external/clang/test/Analysis/
Dfields.c62 struct Bits bits; in testBitfields() local
64 if (foo() && bits.b) // expected-warning {{garbage}} in testBitfields()
66 if (foo() && bits.inner.e) // expected-warning {{garbage}} in testBitfields()
69 bits.c = 1; in testBitfields()
70 clang_analyzer_eval(bits.c == 1); // expected-warning {{TRUE}} in testBitfields()
72 if (foo() && bits.b) // expected-warning {{garbage}} in testBitfields()
74 if (foo() && bits.x) // expected-warning {{garbage}} in testBitfields()
77 bits.x = true; in testBitfields()
78 clang_analyzer_eval(bits.x == true); // expected-warning{{TRUE}} in testBitfields()
79 bits.b = 2; in testBitfields()
[all …]
/external/antlr/antlr-3.4/runtime/JavaScript/src/org/antlr/runtime/
DBitSet.js14 org.antlr.runtime.BitSet = function(bits) { argument
15 if (!bits) {
16 bits = org.antlr.runtime.BitSet.BITS;
19 if (org.antlr.lang.isArray(bits)) {
24 this.bits = bits;
25 } else if(org.antlr.lang.isNumber(bits)) {
26 this.bits = []; property in org.antlr.runtime.BitSet
121 s.bits[n] |= org.antlr.runtime.BitSet.bitMask(i);
168 if (n >= this.bits.length) {
171 this.bits[n] |= org.antlr.runtime.BitSet.bitMask(el);
[all …]
/external/antlr/antlr-3.4/runtime/Perl5/lib/ANTLR/Runtime/
DBitSet.pm46 my $bits;
49 $bits = '0' x BITS;
51 elsif (exists $args->{bits}) {
52 $bits = $args->{bits};
55 $bits = reverse unpack('B*', pack('N', $args->{number}));
66 $bits = '';
68 $bits .= reverse substr(unpack('B*', pack('h', hex $h)), 4);
76 $bits = '0' x $args->{size};
82 $self->bits($bits);
111 my $bits = $self->bits;
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
DSIInstrInfo.td34 field bits<4> EncodingType = 0;
35 field bits<1> NeedWait = 0;
45 field bits<32> Inst;
51 field bits<64> Inst;
94 // i64Literal is really a i32 literal with the top 32-bits all set to zero.
119 bits<4> EN;
120 bits<6> TGT;
121 bits<1> COMPR;
122 bits<1> DONE;
123 bits<1> VM;
[all …]
/external/libogg/src/
Dbitwise.c59 void oggpack_writetrunc(oggpack_buffer *b,long bits){ in oggpack_writetrunc() argument
60 long bytes=bits>>3; in oggpack_writetrunc()
62 bits-=bytes*8; in oggpack_writetrunc()
64 b->endbit=bits; in oggpack_writetrunc()
66 *b->ptr&=mask[bits]; in oggpack_writetrunc()
70 void oggpackB_writetrunc(oggpack_buffer *b,long bits){ in oggpackB_writetrunc() argument
71 long bytes=bits>>3; in oggpackB_writetrunc()
73 bits-=bytes*8; in oggpackB_writetrunc()
75 b->endbit=bits; in oggpackB_writetrunc()
77 *b->ptr&=mask8B[bits]; in oggpackB_writetrunc()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrEnc.td1 class Enc_COPROC_VX_3op_v<bits<15> opc> : OpcodeHexagon {
2 bits<5> dst;
3 bits<5> src1;
4 bits<5> src2;
196 class Enc_COPROC_VX_cmp<bits<13> opc> : OpcodeHexagon {
197 bits<2> dst;
198 bits<5> src1;
199 bits<5> src2;
244 class Enc_COPROC_VX_p2op<bits<5> opc> : OpcodeHexagon {
245 bits<2> src1;
[all …]

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