| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 819 EXTLOAD, enumerator
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| D | BasicTTIImpl.h | 499 LA = getTLI()->getLoadExtAction(ISD::EXTLOAD, LT.second, MemVT); in getMemoryOpCost()
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| D | SelectionDAGNodes.h | 2275 cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 185 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
191 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand); in AMDGPUTargetLowering()
194 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand); in AMDGPUTargetLowering()
197 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand); in AMDGPUTargetLowering()
200 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand); in AMDGPUTargetLowering()
222 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); in AMDGPUTargetLowering()
223 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand); in AMDGPUTargetLowering()
224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand); in AMDGPUTargetLowering()
225 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand); in AMDGPUTargetLowering()
227 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); in AMDGPUTargetLowering()
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| D | SIISelLowering.cpp | 149 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in SITargetLowering()
150 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal); in SITargetLowering()
151 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal); in SITargetLowering()
152 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand); in SITargetLowering()
161 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in SITargetLowering()
163 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand); in SITargetLowering()
164 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand); in SITargetLowering()
562 ExtTy = ISD::EXTLOAD; in LowerParameter()
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| D | R600ISelLowering.cpp | 142 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
143 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
144 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
1563 SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr, in LowerLOAD()
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| D | AMDGPUInstructions.td | 190 L->getExtensionType() == ISD::EXTLOAD;
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 183 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); in WebAssemblyTargetLowering()
186 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD}) in WebAssemblyTargetLowering()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 272 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) && in ExpandConstantFP()
286 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx, in ExpandConstantFP()
387 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, in ExpandUnalignedStore()
506 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, in ExpandUnalignedLoad()
985 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeLoadOps()
1121 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) { in LegalizeLoadOps()
1166 assert(ExtType != ISD::EXTLOAD && in LegalizeLoadOps()
1170 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, in LegalizeLoadOps()
1520 ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, MachinePointerInfo(), in ExpandExtractFromVectorThroughStack()
1688 State.IntValue = DAG.getExtLoad(ISD::EXTLOAD, DL, LoadTy, State.Chain, in getSignAsIntValue()
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| D | LegalizeVectorOps.cpp | 545 ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR, in ExpandLoad()
599 case ISD::EXTLOAD: in ExpandLoad()
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| D | SelectionDAGDumper.cpp | 501 case ISD::EXTLOAD: OS << ", anyext"; break; in print_details()
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| D | DAGCombiner.cpp | 969 : ISD::EXTLOAD) in PromoteOperand()
1191 : ISD::EXTLOAD) in PromoteLoad()
3158 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; in visitAND()
3167 if (Load->getExtensionType() == ISD::EXTLOAD) { in visitAND()
6589 TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) { in visitANY_EXTEND()
6596 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT, in visitANY_EXTEND()
9121 TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) { in visitFP_EXTEND()
9123 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT, in visitFP_EXTEND()
11641 TLI.isLoadExtLegal(ISD::EXTLOAD, LegalizedStoredValueTy, StoreTy) && in MergeConsecutiveStores()
12123 : ISD::EXTLOAD; in ReplaceExtractVectorEltOfLoadWithNarrowedLoad()
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| D | LegalizeIntegerTypes.cpp | 474 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); in PromoteIntRes_LOAD()
2035 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); in ExpandIntRes_LOAD()
3102 ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), FudgePtr, in ExpandIntOp_UINT_TO_FP()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 210 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); in NVPTXTargetLowering()
211 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); in NVPTXTargetLowering()
212 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); in NVPTXTargetLowering()
213 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand); in NVPTXTargetLowering()
214 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand); in NVPTXTargetLowering()
215 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand); in NVPTXTargetLowering()
216 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand); in NVPTXTargetLowering()
217 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand); in NVPTXTargetLowering()
218 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand); in NVPTXTargetLowering()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 129 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in XCoreTargetLowering()
471 SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, in LowerLOAD()
989 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(), in LowerATOMIC_LOAD()
995 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(), in LowerATOMIC_LOAD()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZOperators.td | 373 return Type == ISD::EXTLOAD || Type == ISD::SEXTLOAD;
388 return Type == ISD::EXTLOAD || Type == ISD::ZEXTLOAD;
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| D | SystemZISelLowering.cpp | 243 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in SystemZTargetLowering()
276 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); in SystemZTargetLowering()
415 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand); in SystemZTargetLowering()
3038 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(), in lowerATOMIC_LOAD()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 151 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in BPFTargetLowering()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 240 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in MipsTargetLowering()
248 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in MipsTargetLowering()
249 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); in MipsTargetLowering()
256 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); in MipsTargetLowering()
420 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); in MipsTargetLowering()
2226 (ExtType == ISD::EXTLOAD)) in lowerLOAD()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1458 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Expand); in SparcTargetLowering()
1462 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, VT, Expand); in SparcTargetLowering()
1484 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in SparcTargetLowering()
1485 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand); in SparcTargetLowering()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1709 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand); in HexagonTargetLowering()
1715 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in HexagonTargetLowering()
1778 setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand); in HexagonTargetLowering()
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| D | HexagonISelDAGToDAG.cpp | 381 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD); in SelectIndexedLoad()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 431 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); in AArch64TargetLowering()
432 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in AArch64TargetLowering()
433 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand); in AArch64TargetLowering()
434 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand); in AArch64TargetLowering()
611 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); in AArch64TargetLowering()
679 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT.getSimpleVT(), Expand); in addTypeForNEON()
2511 ExtType = ISD::EXTLOAD; in LowerFormalArguments()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 81 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 389 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); in X86TargetLowering()
390 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); in X86TargetLowering()
391 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand); in X86TargetLowering()
764 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand); in X86TargetLowering()
769 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand); in X86TargetLowering()
892 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom); in X86TargetLowering()
893 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom); in X86TargetLowering()
894 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom); in X86TargetLowering()
895 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom); in X86TargetLowering()
896 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom); in X86TargetLowering()
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