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Searched refs:EndIdx (Results 1 – 9 of 9) sorted by relevance

/external/llvm/lib/Target/AArch64/
DAArch64ExpandPseudoInsts.cpp292 int EndIdx = NotSet; in trySequenceOfOnes() local
302 EndIdx = Idx; in trySequenceOfOnes()
306 if (StartIdx == NotSet || EndIdx == NotSet) in trySequenceOfOnes()
317 if (StartIdx > EndIdx) { in trySequenceOfOnes()
318 std::swap(StartIdx, EndIdx); in trySequenceOfOnes()
333 if ((Idx < StartIdx || EndIdx < Idx) && Chunk != Outside) { in trySequenceOfOnes()
344 } else if (Idx > StartIdx && Idx < EndIdx && Chunk != Inside) { in trySequenceOfOnes()
DAArch64InstrInfo.cpp715 for (unsigned OpIdx = 0, EndIdx = Instr->getNumOperands(); OpIdx < EndIdx; in UpdateOperandRegClass() local
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp866 unsigned StartIdx, EndIdx; member
879 : V(V), RLAmt(R), StartIdx(S), EndIdx(E), Repl32(false), Repl32CR(false), in BitGroup()
1085 BitGroups[BitGroups.size()-1].EndIdx == Bits.size()-1 && in collectBitGroups()
1089 BitGroups[BitGroups.size()-1].EndIdx = BitGroups[0].EndIdx; in collectBitGroups()
1140 if (BG.StartIdx <= BG.EndIdx) { in assignRepl32BitGroups()
1141 for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i) { in assignRepl32BitGroups()
1154 for (unsigned i = 0; i <= BG.EndIdx; ++i) { in assignRepl32BitGroups()
1166 if (BG.StartIdx < 32 && BG.EndIdx < 32) { in assignRepl32BitGroups()
1177 " [" << BG.StartIdx << ", " << BG.EndIdx << "]\n"); in assignRepl32BitGroups()
1189 I->StartIdx == (IP->EndIdx + 1) % 64 && I != IP) { in assignRepl32BitGroups()
[all …]
/external/llvm/utils/TableGen/
DCodeGenRegisters.cpp1554 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); in pruneUnitSets() local
1555 SubIdx != EndIdx; ++SubIdx) { in pruneUnitSets()
1558 for (; SuperIdx != EndIdx; ++SuperIdx) { in pruneUnitSets()
1579 if (SuperIdx == EndIdx) in pruneUnitSets()
1648 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) { in computeRegUnitSets() local
1656 SearchIdx != EndIdx; ++SearchIdx) { in computeRegUnitSets()
1829 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) in computeDerivedInfo() local
1834 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) in computeDerivedInfo() local
1842 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) { in computeDerivedInfo() local
DSubtargetEmitter.cpp975 for (unsigned UseIdx = 0, EndIdx = Reads.size(); in GenSchedClassTables() local
976 UseIdx != EndIdx; ++UseIdx) { in GenSchedClassTables()
/external/llvm/lib/Transforms/InstCombine/
DInstCombineVectorOps.cpp821 unsigned EndIdx = Mask.back(); in isShuffleExtractingFromLHS() local
822 if (BegIdx > EndIdx || EndIdx >= LHSElems || EndIdx - BegIdx != MaskElems - 1) in isShuffleExtractingFromLHS()
/external/llvm/lib/CodeGen/
DPostRASchedulerList.cpp152 void setEndIndex(unsigned EndIdx) { EndIndex = EndIdx; } in setEndIndex() argument
DLiveInterval.cpp790 SlotIndex EndIdx = Indexes.getMBBEndIdx(MBB); in searchForVNI() local
793 LiveRange::iterator I = LR.find(EndIdx.getPrevSlot()); in searchForVNI()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp8144 int EndIdx = in lowerVectorShuffleAsBroadcast() local
8146 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) { in lowerVectorShuffleAsBroadcast()