| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrFP.td | 16 def SelectF64 : SelectWrapper<FP64>;
21 defm CondStoreF64 : CondStores<FP64, nonvolatile_store,
31 def LZDR : InherentRRE<"lzdr", 0xB375, FP64, (fpimm0)>;
38 def LDR : UnaryRR <"ld", 0x28, null_frag, FP64, FP64>;
46 defm LTDBR : LoadAndTestRRE<"ltdb", 0xB312, FP64>;
54 defm : CompareZeroFP<LTDBRCompare, FP64>;
62 def LTDBRCompare_VecPseudo : Pseudo<(outs), (ins FP64:$R1, FP64:$R2), []>;
67 defm : CompareZeroFP<LTDBRCompare_VecPseudo, FP64>;
72 def LGDR : UnaryRRE<"lgd", 0xB3CD, bitconvert, GR64, FP64>;
73 def LDGR : UnaryRRE<"ldg", 0xB3C1, bitconvert, FP64, GR64>;
[all …]
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| D | SystemZRegisterInfo.td | 210 defm FP64 : SystemZRegClass<"FP64", [f64], 64, (sequence "F%uD", 0, 15)>;
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| D | SystemZInstrVector.td | 1004 defm : ScalarToVectorFP<VREPG, v2f64, FP64, subreg_r64>;
1010 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 0),
1011 (VPDI (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt,
1013 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 1),
1014 (VPDI VR128:$vec, (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt,
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 413 FP64 = 0x00400000 enumerator
989 FCMP_d = FPCompareFixed | FP64 | 0x00000000,
992 FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008,
995 FCMPE_d = FPCompareFixed | FP64 | 0x00000010,
997 FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018
1006 FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000,
1009 FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010,
1019 FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000,
1029 FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000
1038 FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000,
[all …]
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| D | simulator-arm64.cc | 2392 unsigned reg_size = (instr->Mask(FP64) == FP64) ? kDRegSizeInBits in VisitFPCompare()
2415 unsigned reg_size = (instr->Mask(FP64) == FP64) ? kDRegSizeInBits in VisitFPConditionalCompare()
3183 if (instr->Mask(FP64) == FP64) { in FPProcessNaNs()
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| D | assembler-arm64-inl.h | 1217 return fd.Is64Bits() ? FP64 : FP32;
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| /external/vixl/src/vixl/a64/ |
| D | constants-a64.h | 399 FP64 = 0x00400000 enumerator
419 NEON_FP_2D = FP64 | NEON_Q
1093 FCMP_d = FPCompareFixed | FP64 | 0x00000000,
1096 FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008,
1099 FCMPE_d = FPCompareFixed | FP64 | 0x00000010,
1102 FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018,
1112 FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000,
1115 FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010,
1125 FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000,
1135 FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000
[all …]
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| D | simulator-a64.cc | 2163 VectorFormat vform = (instr->Mask(FP64) == FP64) ? kFormatD : kFormatS; in VisitFPDataProcessing1Source()
2211 VectorFormat vform = (instr->Mask(FP64) == FP64) ? kFormatD : kFormatS; in VisitFPDataProcessing2Source()
2279 if (instr->Mask(FP64) == FP64) { in FPProcessNaNs()
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| /external/llvm/test/CodeGen/Mips/ |
| D | fastcc.ll | 5 … -march=mipsel -mcpu=mips32r2 -mattr=+fp64,+nooddspreg | FileCheck %s -check-prefix=FP64-NOODDSPREG
356 ; FP64-NOODDSPREG-LABEL: caller3:
361 ; FP64-NOODDSPREG-DAG: lw $[[R0:[0-9]+]], %got(da)(${{[0-9]+|gp}})
362 ; FP64-NOODDSPREG-DAG: ldc1 $f0, 0($[[R0]])
363 ; FP64-NOODDSPREG-DAG: ldc1 $f2, 8($[[R0]])
364 ; FP64-NOODDSPREG-DAG: ldc1 $f4, 16($[[R0]])
365 ; FP64-NOODDSPREG-DAG: ldc1 $f6, 24($[[R0]])
366 ; FP64-NOODDSPREG-DAG: ldc1 $f8, 32($[[R0]])
367 ; FP64-NOODDSPREG-DAG: ldc1 $f10, 40($[[R0]])
368 ; FP64-NOODDSPREG-DAG: ldc1 $f12, 48($[[R0]])
[all …]
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| D | 2013-11-18-fp64-const0.ll | 2 ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck -check-prefix=CHECK-FP64 %s
6 ; It originally failed on MIPS32 with FP64 with the following error:
16 ; CHECK-FP64: mtc1 $zero, $f{{[0-9]+}}
17 ; CHECK-FP64-NOT: mtc1 $zero,
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| D | fp64a.ll | 9 ; FIXME: We currently don't test that attempting to use FP64 on MIPS32r1 is an
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| /external/llvm/test/CodeGen/Mips/cconv/ |
| D | callee-saved-fpxx1.ll | 1 ; RUN: llc -march=mips -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=O32-FP64-INV %s
2 ; RUN: llc -march=mipsel -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=O32-FP64-INV %s
20 ; O32-FP64-INV-NOT: sdc1 $f20,
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| D | return-hard-float.ll | 13 …cation-model=static -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=ALL --check-prefix=032FP64 %s
14 …cation-model=static -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=ALL --check-prefix=032FP64 %s
58 ; 032FP64-DAG: ldc1 $f0, 0($sp)
59 ; 032FP64-DAG: ldc1 $f2, 8($sp)
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | default-fp-mode.ll | 1 …=SI -mattr=-fp32-denormals,+fp64-denormals < %s | FileCheck -check-prefix=FP64-DENORMAL -check-pre…
8 …nga -mattr=-fp32-denormals,+fp64-denormals < %s | FileCheck -check-prefix=FP64-DENORMAL -check-pre…
21 ; FP64-DENORMAL: FloatMode: 192
22 ; FP64-DENORMAL: IeeeMode: 0
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegisterInfo.td | 32 def FP64 : WebAssemblyReg<"%FP64">;
56 def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64)>;
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| D | WebAssemblyRegisterInfo.cpp | 49 WebAssembly::FP64}) in getReservedRegs()
93 /* hasFP */ {WebAssembly::FP32, WebAssembly::FP64}}; in getFrameRegister()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.h | 111 MachineBasicBlock::iterator I, bool FP64) const;
113 MachineBasicBlock::iterator I, bool FP64) const;
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| D | MipsSEFrameLowering.cpp | 69 MachineBasicBlock::iterator I, bool FP64) const;
71 MachineBasicBlock::iterator I, bool FP64) const;
270 bool FP64) const { in expandBuildPairF64()
284 (FP64 && !Subtarget.useOddSPReg())) { in expandBuildPairF64()
297 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandBuildPairF64()
322 bool FP64) const { in expandExtractElementF64()
346 (FP64 && !Subtarget.useOddSPReg())) { in expandExtractElementF64()
359 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandExtractElementF64()
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| D | MipsSEInstrInfo.cpp | 588 bool FP64) const { in expandExtractElementF64()
619 BuildMI(MBB, I, dl, get(FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32), DstReg) in expandExtractElementF64()
627 bool FP64) const { in expandBuildPairF64()
672 BuildMI(MBB, I, dl, get(FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32), DstReg) in expandBuildPairF64()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUSubtarget.h | 67 bool FP64; variable
139 return FP64; in hasHWFP64()
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| D | AMDGPUSubtarget.cpp | 69 TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false), in AMDGPUSubtarget()
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| D | AMDGPU.td | 46 "FP64",
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| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | call.ll | 174 ; for FP64.
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| /external/llvm/test/MC/SystemZ/ |
| D | regs-bad.s | 116 # Test FP64 operands
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| /external/valgrind/coregrind/ |
| D | m_machine.c | 1584 # define FP64 22 in VG_() macro
1661 if (FIR & (1 << FP64)) { in VG_()
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