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Searched refs:FPSCR (Results 1 – 14 of 14) sorted by relevance

/external/valgrind/none/tests/arm/
Dvfp.stdout.exp726 vcmp.f64 d0, d19 :: FPSCR 0x80000000 Dd 0xc00ba752 5460aa65 Dm 0xc004fef9 db22d0e5
727 vcmp.f64 d11, d16 :: FPSCR 0x20000000 Dd 0x40d6ecdc cccccccd Dm 0x40aac300 00000000
728 vcmp.f64 d21, d30 :: FPSCR 0x20000000 Dd 0xc0b1ac80 00000000 Dm 0xc11b9be6 00000000
729 vcmp.f64 d7, d28 :: FPSCR 0x20000000 Dd 0x407a9800 00000000 Dm 0xc07c84cc cccccccd
730 vcmp.f64 d29, d3 :: FPSCR 0x20000000 Dd 0x7ff00000 00000000 Dm 0x40e0e04e 66666666
731 vcmp.f64 d3, d22 :: FPSCR 0x60000000 Dd 0x40000000 00000000 Dm 0x40000000 00000000
732 vcmp.f64 d3, d22 :: FPSCR 0x60000000 Dd 0x40280bc6 a7ef9db2 Dm 0x40280bc6 a7ef9db2
733 vcmp.f64 d3, d22 :: FPSCR 0x60000000 Dd 0x00000000 00000000 Dm 0x00000000 00000000
734 vcmp.f64 d9, d2 :: FPSCR 0x60000000 Dd 0x7ff00000 00000000 Dm 0x7ff00000 00000000
735 vcmp.f64 d30, d15 :: FPSCR 0x60000000 Dd 0xfff00000 00000000 Dm 0xfff00000 00000000
[all …]
/external/valgrind/none/tests/ppc64/
Dtest_dfp1.stdout.exp571 Test move to/from FPSCR
572 FPSCR binary floating point rounding mode 0000000000000000 == 0000000000000000? yes
573 FPSCR binary floating point rounding mode 0000000000000001 == 0000000000000001? yes
574 FPSCR binary floating point rounding mode 0000000000000002 == 0000000000000002? yes
575 FPSCR binary floating point rounding mode 0000000000000003 == 0000000000000003? yes
576 FPSCR decimal floating point rounding mode 0000000000000003 == 0000000000000003? yes
577 FPSCR decimal floating point rounding mode 0000000100000003 == 0000000100000003? yes
578 FPSCR decimal floating point rounding mode 0000000200000003 == 0000000200000003? yes
579 FPSCR decimal floating point rounding mode 0000000300000003 == 0000000300000003? yes
580 FPSCR decimal floating point rounding mode 0000000400000003 == 0000000400000003? yes
[all …]
/external/valgrind/none/tests/ppc32/
Dtest_dfp1.stdout.exp571 Test move to/from FPSCR
572 FPSCR binary floating point rounding mode 0000000000000000 == 0000000000000000? yes
573 FPSCR binary floating point rounding mode 0000000000000001 == 0000000000000001? yes
574 FPSCR binary floating point rounding mode 0000000000000002 == 0000000000000002? yes
575 FPSCR binary floating point rounding mode 0000000000000003 == 0000000000000003? yes
576 FPSCR decimal floating point rounding mode 0000000000000003 == 0000000000000003? yes
577 FPSCR decimal floating point rounding mode 0000000100000003 == 0000000100000003? yes
578 FPSCR decimal floating point rounding mode 0000000200000003 == 0000000200000003? yes
579 FPSCR decimal floating point rounding mode 0000000300000003 == 0000000300000003? yes
580 FPSCR decimal floating point rounding mode 0000000400000003 == 0000000400000003? yes
[all …]
/external/llvm/lib/Target/ARM/
DARMRegisterInfo.td159 // We model fpscr with two registers: FPSCR models the control bits and will be
167 def FPSCR : ARMReg<3, "fpscr">;
169 let Aliases = [FPSCR];
DARMInstrVFP.td1183 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
1184 let Uses = [FPSCR] in {
1673 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
1679 // Application level FPSCR -> GPR
1680 let hasSideEffects = 1, Uses = [FPSCR] in
1686 let Uses = [FPSCR] in {
1724 let Defs = [FPSCR] in {
1725 // Application level GPR -> FPSCR
DARMBaseRegisterInfo.cpp136 Reserved.set(ARM::FPSCR); in getReservedRegs()
DARMScheduleSwift.td640 // 4.2.38 Advanced SIMD and VFP, Move FPSCR
DARMISelLowering.cpp4329 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, in LowerFLT_ROUNDS_() local
4332 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR, in LowerFLT_ROUNDS_()
/external/valgrind/VEX/priv/
Dhost_arm_defs.c1362 i->ARMin.FPSCR.toFPSCR = toFPSCR; in ARMInstr_FPSCR()
1363 i->ARMin.FPSCR.iReg = iReg; in ARMInstr_FPSCR()
1845 if (i->ARMin.FPSCR.toFPSCR) { in ppARMInstr()
1847 ppHRegARM(i->ARMin.FPSCR.iReg); in ppARMInstr()
1850 ppHRegARM(i->ARMin.FPSCR.iReg); in ppARMInstr()
2229 if (i->ARMin.FPSCR.toFPSCR) in getRegUsage_ARMInstr()
2230 addHRegUse(u, HRmRead, i->ARMin.FPSCR.iReg); in getRegUsage_ARMInstr()
2232 addHRegUse(u, HRmWrite, i->ARMin.FPSCR.iReg); in getRegUsage_ARMInstr()
2439 i->ARMin.FPSCR.iReg = lookupHRegRemap(m, i->ARMin.FPSCR.iReg); in mapRegs_ARMInstr()
3763 Bool toFPSCR = i->ARMin.FPSCR.toFPSCR; in emit_ARMInstr()
[all …]
Dhost_arm_defs.h852 } FPSCR; member
/external/libunwind/src/ptrace/
D_UPT_reg_offset.c423 [UNW_PPC32_FPSCR] = UNW_PPC_PT(FPSCR), \
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.td100 // Extract FPSCR (not modeled at the DAG level).
2327 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
/external/valgrind/memcheck/
Dmc_machine.c868 if (o == GOF(FPSCR) && sz == 4) return -1; in get_otrack_shadow_offset_wrk()
/external/v8/
DChangeLog12028 Avoided trashing the FPSCR when calculating Math.floor on ARM.