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Searched refs:FRC (Results 1 – 21 of 21) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dllvm.AMDGPU.fract.f64.ll9 ; GCN: v_fract_f64_e32 [[FRC:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
12 ; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
17 ; CI: buffer_store_dwordx2 [[FRC]]
26 ; GCN: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
29 ; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
34 ; CI: buffer_store_dwordx2 [[FRC]]
44 ; GCN: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -|v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]|
47 ; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
52 ; CI: buffer_store_dwordx2 [[FRC]]
/external/llvm/lib/Target/PowerPC/
DPPCInstrQPX.td40 : AForm_1<opcode, xo, (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC),
41 !strconcat(opc, " $FRT, $FRA, $FRC, $FRB"), IIC_FPFused,
42 [(set v4f64:$FRT, (IntID v4f64:$FRA, v4f64:$FRB, v4f64:$FRC))]>;
45 : AForm_1<opcode, xo, (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC),
46 !strconcat(opc, " $FRT, $FRA, $FRC, $FRB"), IIC_VecPerm,
47 [(set v4f64:$FRT, (IntID v4f64:$FRA, v4f64:$FRB, v4f64:$FRC))]>;
55 : AForm_3<opcode, xo, (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC),
56 !strconcat(opc, " $FRT, $FRA, $FRC"), IIC_FPGeneral,
57 [(set v4f64:$FRT, (IntID v4f64:$FRA, v4f64:$FRC))]>;
156 (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC),
[all …]
DPPCInstrInfo.td2443 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2444 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2445 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2447 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2448 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2449 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2451 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2452 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2454 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2456 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
[all …]
DPPCInstrFormats.td1315 bits<5> FRC;
1325 let Inst{21-25} = FRC;
1333 let FRC = 0;
1365 let FRC = 0;
/external/clang/test/Profile/
Dobjc-general.m34 // PGOGEN: @[[FRC:"__profc_objc_general.m_\+\[A foreach_\]"]] = private global [2 x i64] zeroinitia…
45 // PGOGEN: store {{.*}} @[[FRC]], i64 0, i64 0
49 // PGOGEN: store {{.*}} @[[FRC]], i64 0, i64 1
/external/mesa3d/src/gallium/tests/graw/fragment-shader/
Dfrag-frc.sh11 FRC OUT[0], TEMP[0]
/external/mesa3d/src/gallium/tests/graw/vertex-shader/
Dvert-frc.sh13 FRC OUT[1], TEMP[0]
/external/llvm/lib/Target/X86/
DX86InstrAVX512.td113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
1474 (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, AVXCC:$cc),
1477 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1478 _.FRC:$src2,
1484 (ins _.FRC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1487 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
2966 (ins _.RC:$src1, _.FRC:$src2),
2969 (scalar_to_vector _.FRC:$src2))))],
2972 def rm : AVX512PI<0x10, MRMSrcMem, (outs _.FRC:$dst), (ins _.ScalarMemOp:$src),
2974 [(set _.FRC:$dst, (_.ScalarLdFrag addr:$src))],
[all …]
/external/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_opcode_tmp.h64 OP11(FRC)
/external/mesa3d/src/mesa/program/
Dprogram_lexer.l204 FRC{sz}{cc}{sat} { return_opcode( 1, VECTOR_OP, FRC, 3); }
/external/llvm/lib/Target/Hexagon/
DHexagonBitSimplify.cpp1299 const TargetRegisterClass *FRC = HBS::getFinalVRegClass(RD, MRI); in processBlock() local
1300 unsigned NewR = MRI.createVirtualRegister(FRC); in processBlock()
1561 auto *FRC = HBS::getFinalVRegClass(MR, MRI); in processBlock() local
1562 unsigned NewR = MRI.createVirtualRegister(FRC); in processBlock()
2150 const TargetRegisterClass *FRC = HBS::getFinalVRegClass(RD, MRI); in processBlock() local
2153 if (FRC->getID() == Hexagon::DoubleRegsRegClassID) { in processBlock()
2159 if (FRC->getID() == Hexagon::IntRegsRegClassID) { in processBlock()
2167 if (FRC->getID() == Hexagon::PredRegsRegClassID) { in processBlock()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_vec4.h352 vec4_instruction *FRC(dst_reg dst, src_reg src0);
Dbrw_eu.h866 ALU1(FRC)
Dbrw_vec4_visitor.cpp110 ALU1(FRC) in ALU1()
1267 inst = emit(FRC(result_dst, op[0])); in visit()
Dbrw_eu_emit.c893 ALU1(FRC) in ALU2()
/external/mesa3d/src/gallium/state_trackers/d3d1x/gd3d1x/
Dsm4_to_tgsi.cpp265 OP1(FRC); in translate_insns()
/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_vertprog.c81 OPN(FRC, 1),
/external/mesa3d/src/gallium/drivers/nv30/
Dnvfx_vertprog.c608 nvfx_vp_emit(vpc, arith(sat, VEC, FRC, dst, mask, src[0], none, none)); in nvfx_vertprog_parse_instruction()
Dnvfx_fragprog.c606 nvfx_fp_emit(fpc, arith(sat, FRC, dst, mask, src[0], none, none)); in nvfx_fragprog_parse_instruction()
/external/llvm/docs/
DCodeGenerator.rst995 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
996 "fmadds $FRT, $FRA, $FRC, $FRB",
997 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
/external/mesa3d/src/gallium/docs/source/
Dtgsi.rst292 .. opcode:: FRC - Fraction