| /external/llvm/test/TableGen/ |
| D | cast.td | 72 multiclass arith<bits<8> opcode, string asmstr, string Intr> {
75 … [(set VR128:$dst, (!cast<Intrinsic>(!strconcat(Intr, "_ps")) VR128:$src1, VR128:$src2))]>;
79 … [(set VR128:$dst, (!cast<Intrinsic>(!strconcat(Intr, "_pd")) VR128:$src1, VR128:$src2))]>;
84 class IntInst<bits<8> opcode, string asmstr, Intrinsic Intr> :
87 [(set VR128:$dst, (Intr VR128:$src1, VR128:$src2))]>;
90 multiclass arith_int<bits<8> opcode, string asmstr, string Intr> {
91 def PS_Int : IntInst<opcode, asmstr, !cast<Intrinsic>(!strconcat(Intr, "_ps"))>;
93 def PD_Int : IntInst<opcode, asmstr, !cast<Intrinsic>(!strconcat(Intr, "_pd"))>;
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUPromoteAlloca.cpp | 376 IntrinsicInst *Intr = dyn_cast<IntrinsicInst>(Call); in visitAlloca() local
377 if (!Intr) { in visitAlloca()
393 Builder.SetInsertPoint(Intr); in visitAlloca()
394 switch (Intr->getIntrinsicID()) { in visitAlloca()
398 Intr->eraseFromParent(); in visitAlloca()
401 MemCpyInst *MemCpy = cast<MemCpyInst>(Intr); in visitAlloca()
405 Intr->eraseFromParent(); in visitAlloca()
409 MemSetInst *MemSet = cast<MemSetInst>(Intr); in visitAlloca()
413 Intr->eraseFromParent(); in visitAlloca()
417 Intr->dump(); in visitAlloca()
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| D | SIISelLowering.cpp | 1031 SDNode *Intr = BRCOND.getOperand(1).getNode(); in LowerBRCOND() local
1035 if (Intr->getOpcode() == ISD::SETCC) { in LowerBRCOND()
1037 SDNode *SetCC = Intr; in LowerBRCOND()
1041 Intr = SetCC->getOperand(0).getNode(); in LowerBRCOND()
1049 assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN); in LowerBRCOND()
1052 ArrayRef<EVT> Res(Intr->value_begin() + 1, Intr->value_end()); in LowerBRCOND()
1057 Ops.append(Intr->op_begin() + 1, Intr->op_end()); in LowerBRCOND()
1079 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) { in LowerBRCOND()
1080 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg); in LowerBRCOND()
1095 SDValue(Intr, Intr->getNumValues() - 1), in LowerBRCOND()
[all …]
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| /external/clang/utils/TableGen/ |
| D | NeonEmitter.cpp | 469 Intrinsic &Intr; member in __anon985e31310111::Intrinsic::DagEmitter
473 DagEmitter(Intrinsic &Intr, StringRef CallPrefix) : in DagEmitter() argument
474 Intr(Intr), CallPrefix(CallPrefix) { in DagEmitter()
1495 Intrinsic &Callee = Intr.Emitter.getIntrinsic(N, Types); in emitDagCall()
1499 Intr.Dependencies.insert(&Callee); in emitDagCall()
1529 assert_with_loc(Intr.Variables.find(DI->getArgName(ArgIdx)) != in emitDagCast()
1530 Intr.Variables.end(), in emitDagCast()
1532 castToType = Intr.Variables[DI->getArgName(ArgIdx)].getType(); in emitDagCast()
1538 castToType = Intr.getReturnType(); in emitDagCast()
1562 while (Intr.Variables.find(N) != Intr.Variables.end()) in emitDagCast()
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonOptimizeSZextends.cpp | 121 Value *Intr = Shl->getOperand(0); in runOnFunction() local
129 if (IntrinsicInst *I = dyn_cast<IntrinsicInst>(Intr)) { in runOnFunction()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 2172 static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) { in lowerMSALoadIntr() argument
2188 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue(); in lowerINTRINSIC_W_CHAIN() local
2189 switch (Intr) { in lowerINTRINSIC_W_CHAIN()
2236 return lowerMSALoadIntr(Op, DAG, Intr); in lowerINTRINSIC_W_CHAIN()
2240 static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) { in lowerMSAStoreIntr() argument
2256 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue(); in lowerINTRINSIC_VOID() local
2257 switch (Intr) { in lowerINTRINSIC_VOID()
2264 return lowerMSAStoreIntr(Op, DAG, Intr); in lowerINTRINSIC_VOID()
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| /external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/textana/en-GB/ |
| D | en-GB_lexpos.utf | 450 ADJ "intravenous" "Intr@v'i:n@s"
452 ADJ "introductory" "Intr@d'Vkt@rI"
1354 ADJ^N_ING^V "introducing" "Intr@dj'u:sIN"
2965 N "introduction" "Intr@d'VkS@n"
2966 N "introvert" "'Intr@v3t"
2967 N "introverts" "'Intr@v3ts"
4911 V "entrance" "Intr'A:ns"
4912 V "entrances" "Intr'A:nsIz"
5056 V "introduce" "Intr@dj'u:s"
5057 V "introduced" "Intr@dj'u:sd"
[all …]
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| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 22 // Intr*Mem - Memory properties. An intrinsic is allowed to have at most one of
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrSSE.td | 3353 ComplexPattern mem_cpat, Intrinsic Intr,
3385 def : Pat<(Intr VR128:$src),
3387 def : Pat<(Intr (load addr:$src)),
3390 def : Pat<(Intr mem_cpat:$src),
3400 Intrinsic Intr, SDNode OpNode, Domain d,
3433 def : Pat<(Intr VR128:$src),
3437 def : Pat<(Intr mem_cpat:$src),
3563 multiclass scalar_unary_math_patterns<Intrinsic Intr, string OpcPrefix,
3567 def : Pat<(VT (Move VT:$dst, (Intr VT:$src))),
3573 def : Pat<(VT (X86Blendi VT:$dst, (Intr VT:$src), (i8 1))),
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 10322 Intrinsic::ID Intr, IntrLD, IntrPerm; in PerformDAGCombine() local
10325 Intr = isLittleEndian ? Intrinsic::ppc_altivec_lvsr : in PerformDAGCombine()
10333 Intr = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlpcld : in PerformDAGCombine()
10343 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, PermCntlTy); in PerformDAGCombine()
10429 Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr in PerformDAGCombine() local
10431 if ((IID == Intr || in PerformDAGCombine()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 1420 SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops); in emitIntrinsicWithChainAndGlue() local
1422 SDValue NewChain = SDValue(Intr.getNode(), 0); in emitIntrinsicWithChainAndGlue()
1424 return Intr; in emitIntrinsicWithChainAndGlue()
|