Searched refs:LD1 (Results 1 – 25 of 25) sorted by relevance
121 LD1 {v0.s}[0],[x0] //vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)125 LD1 {v0.s}[0],[x7],x2 //vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)128 LD1 {v0.s}[0],[x7],x2 //vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)131 LD1 {v0.s}[0],[x7],x2 //vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)152 LD1 {v0.s}[0],[x0] //vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)156 LD1 {v0.s}[0],[x7],x2 //vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)176 LD1 {v0.8b},[x0],#8 //vld1_u8(pu1_src_tmp)179 LD1 {v1.8b},[x7],x2 //vld1_u8(pu1_src_tmp)182 LD1 {v2.8b},[x7],x2 //vld1_u8(pu1_src_tmp)184 LD1 {v3.8b},[x7],x2 //vld1_u8(pu1_src_tmp)[all …]
100 LD1 {v1.8b},[x14],#8 //band_table.val[0]103 LD1 {v2.8b},[x14],#8 //band_table.val[1]110 LD1 {v3.8b},[x14],#8 //band_table.val[2]114 LD1 {v4.8b},[x14],#8 //band_table.val[3]118 LD1 {v0.8b},[x4],#8 //Load pu1_src[(ht - 1) * src_strd + col]123 LD1 {v30.8b},[x6] //pi1_sao_offset load205 LD1 {v13.8b},[x4] //au1_cur_row = vld1_u8(pu1_src_cpy)208 LD1 {v15.8b},[x5] //au1_cur_row = vld1_u8(pu1_src_cpy)210 LD1 {v17.8b},[x6] //au1_cur_row = vld1_u8(pu1_src_cpy)212 LD1 {v19.8b},[x10] //au1_cur_row = vld1_u8(pu1_src_cpy)
116 LD1 {v6.8b},[x14] //edge_idx_tbl = vld1_s8(gi1_table_edge_idx)117 LD1 {v7.8b},[x6] //offset_tbl = vld1_s8(pi1_sao_offset)131 …LD1 {v1.16b},[x9],#16 //pu1_top_row = vld1q_u8(pu1_src_top_cpy || pu1_src - src_…132 LD1 {v3.16b},[x0],#16 //pu1_cur_row = vld1q_u8(pu1_src)134 LD1 {v30.16b},[x12],#16 //vld1q_u8(pu1_src[(ht - 1) * src_strd])145 LD1 {v18.16b},[x10] //pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)149 LD1 {v30.16b},[x6] //II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)222 LD1 {v18.16b},[x10] //pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)267 …LD1 {v1.16b},[x9],#16 //pu1_top_row = vld1q_u8(pu1_src_top_cpy || pu1_src - src_…268 LD1 {v3.16b},[x0],#16 //pu1_cur_row = vld1q_u8(pu1_src)[all …]
136 LD1 {v6.8b},[x14] //edge_idx_tbl = vld1_s8(gi1_table_edge_idx)137 LD1 {v7.8b},[x6] //offset_tbl_u = vld1_s8(pi1_sao_offset_u)138 LD1 {v1.8b},[x7] //offset_tbl_v = vld1_s8(pi1_sao_offset_v)152 …LD1 {v28.16b},[x11],#16 //pu1_top_row = vld1q_u8(pu1_src_top_cpy || pu1_src - src_…154 LD1 {v3.16b},[x0],#16 //pu1_cur_row = vld1q_u8(pu1_src)157 LD1 {v30.16b},[x12],#16 //vld1q_u8(pu1_src[(ht - 1) * src_strd])169 LD1 {v18.16b},[x10] //pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)176 LD1 {v30.16b},[x6] //II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)270 LD1 {v18.16b},[x10] //pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)327 …LD1 {v28.16b},[x11] //pu1_top_row = vld1q_u8(pu1_src_top_cpy || pu1_src - src_…[all …]
114 LD1 {v1.8b},[x14],#8 //band_table_u.val[0]119 LD1 {v2.8b},[x14],#8 //band_table_u.val[1]123 LD1 {v3.8b},[x14],#8 //band_table_u.val[2]131 LD1 {v4.8b},[x14],#8 //band_table_u.val[3]135 LD1 {v0.8b},[x4],#8 //Load pu1_src[(ht - 1) * src_strd + col]140 LD1 {v30.8b},[x7] //pi1_sao_offset_u load160 LD1 {v9.8b},[x14],#8 //band_table_v.val[0]163 LD1 {v10.8b},[x14],#8 //band_table_v.val[1]219 LD1 {v11.8b},[x14],#8 //band_table_v.val[2]222 LD1 {v12.8b},[x14],#8 //band_table_v.val[3][all …]
108 LD1 {v0.8b},[x11],#8 //pu1_src[(ht - 1) * src_strd + col]209 LD1 {v7.8b},[x6] //offset_tbl = vld1_s8(pi1_sao_offset)216 LD1 {v6.8b},[x11] //edge_idx_tbl = vld1_s8(gi1_table_edge_idx)258 …LD1 {v3.16b},[x8] //pu1_top_row = vld1q_u8(pu1_src - src_strd - 1) || vld1q_…262 LD1 {v5.16b},[x0] //pu1_cur_row = vld1q_u8(pu1_src)288 LD1 {v16.16b},[x8] //I pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)354 LD1 {v16.16b},[x8] //II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)358 LD1 {v30.16b},[x11] //III pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)470 LD1 {v16.16b},[x8] //pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)575 …LD1 {v3.16b},[x8] //pu1_top_row = vld1q_u8(pu1_src - src_strd - 1) || vld1q_…[all …]
119 LD1 {v0.8b},[x11],#8 //pu1_src[(ht - 1) * src_strd + col]306 LD1 {v6.8b},[x6] //offset_tbl_u = vld1_s8(pi1_sao_offset_u)308 LD1 {v7.8b},[x6] //offset_tbl_v = vld1_s8(pi1_sao_offset_v)344 LD1 {v5.16b},[x0] //pu1_cur_row = vld1q_u8(pu1_src)355 LD1 {v3.16b},[x8] //pu1_top_row = vld1q_u8(pu1_src - src_strd + 2)386 LD1 {v16.16b},[x11] //I pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)428 LD1 {v28.8b},[x2] //edge_idx_tbl = vld1_s8(gi1_table_edge_idx)480 LD1 {v16.16b},[x11] //II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)490 LD1 {v30.16b},[x4] //III pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)505 LD1 {v21.8b},[x2] //edge_idx_tbl = vld1_s8(gi1_table_edge_idx)[all …]
122 LD1 {v0.8b},[x11],#8 //pu1_src[(ht - 1) * src_strd + col]311 LD1 {v6.8b},[x6] //offset_tbl_u = vld1_s8(pi1_sao_offset_u)320 LD1 {v7.8b},[x6] //offset_tbl_v = vld1_s8(pi1_sao_offset_v)353 LD1 {v5.16b},[x0] //pu1_cur_row = vld1q_u8(pu1_src)369 …LD1 {v3.16b},[x8] //pu1_top_row = vld1q_u8(pu1_src - src_strd - 2) || vld1q_…394 LD1 {v16.16b},[x8] //I pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)442 LD1 {v30.8b},[x2] //edge_idx_tbl = vld1_s8(gi1_table_edge_idx)490 LD1 {v16.16b},[x8] //II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)493 LD1 {v30.16b},[x11] //III pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)544 LD1 {v22.8b},[x2] //edge_idx_tbl = vld1_s8(gi1_table_edge_idx)[all …]
108 LD1 {v0.8b},[x11],#8 //pu1_src[(ht - 1) * src_strd + col]221 LD1 {v7.8b},[x6] //offset_tbl = vld1_s8(pi1_sao_offset)233 LD1 {v6.8b},[x6] //edge_idx_tbl = vld1_s8(gi1_table_edge_idx)272 LD1 {v3.16b},[x8] //pu1_top_row = vld1q_u8(pu1_src - src_strd + 1)276 LD1 {v5.16b},[x0] //pu1_cur_row = vld1q_u8(pu1_src)298 LD1 {v16.16b},[x8] //I pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)368 LD1 {v16.16b},[x8] //II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)372 LD1 {v30.16b},[x2] //III pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)494 LD1 {v16.16b},[x8] //pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)600 LD1 {v3.16b},[x8] //pu1_top_row = vld1q_u8(pu1_src - src_strd + 1)[all …]
100 LD1 {v5.8b},[x14] //edge_idx_tbl = vld1_s8(gi1_table_edge_idx)104 LD1 {v7.8b},[x8] //offset_tbl = vld1_s8(pi1_sao_offset)110 LD1 {v0.8b},[x4],#8 //Load pu1_src[(ht - 1) * src_strd + col]145 LD1 {v17.16b},[x12],x1 //pu1_cur_row = vld1q_u8(pu1_src_cpy)152 LD1 {v26.16b},[x12] //II Iteration pu1_cur_row = vld1q_u8(pu1_src_cpy)290 LD1 {v17.16b},[x12] //pu1_cur_row = vld1q_u8(pu1_src_cpy)
118 LD1 {v7.8b},[x8] //offset_tbl = vld1_s8(pi1_sao_offset_u)122 LD1 {v5.8b},[x14] //edge_idx_tbl = vld1_s8(gi1_table_edge_idx)126 LD1 {v0.8b},[x4],#8 //Load pu1_src[(ht - 1) * src_strd + col]133 LD1 {v0.8b},[x5] //offset_tbl = vld1_s8(pi1_sao_offset_v)165 LD1 {v19.16b},[x12],x1 //pu1_cur_row = vld1q_u8(pu1_src_cpy)174 LD1 {v30.16b},[x12] //II Iteration pu1_cur_row = vld1q_u8(pu1_src_cpy)349 LD1 {v19.16b},[x12],x1 //pu1_cur_row = vld1q_u8(pu1_src_cpy)358 LD1 {v30.16b},[x12] //II pu1_cur_row = vld1q_u8(pu1_src_cpy)
83 LD1 {v0.8b},[x1],#8112 LD1 {v0.8b},[x1],#8
114 LD1 {v0.8b},[x0],#8115 LD1 {v1.8b},[x0],#8116 LD1 {v2.8b},[x0],#8117 LD1 {v3.8b},[x0],#8134 LD1 {v0.8b},[x0],#8135 LD1 {v1.8b},[x0],#8136 LD1 {v2.8b},[x0],#8137 LD1 {v3.8b},[x0],#8172 LD1 {v0.8b},[x1],#8173 LD1 {v1.8b},[x1],#8[all …]
165 LD1 {v2.8b, v3.8b},[x1],#16 ////LOAD 8 VALUES OF UV193 LD1 {v2.8b, v3.8b},[x1],#16 ////LOAD 8 VALUES OF U
7 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]10 ; CHECK-LE-DAG: vmov r2, r3, [[LD1]]23 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]26 ; CHECK-LE-DAG: vmov r2, r3, [[LD1]]40 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]43 ; CHECK-LE: vmov r2, r3, [[LD1]]57 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]60 ; CHECK-LE: vmov r2, r3, [[LD1]]73 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]76 ; CHECK-LE: vmov r2, r3, [[LD1]][all …]
52 ``LDR`` and ``LD1``66 Big endian vector load using ``LD1``. Note that the lanes retain the correct ordering.69 Because of this, the instruction ``LD1`` performs a vector load but performs byte swapping not on t…71 It may seem that ``LD1`` should suffice to peform vector loads on a big endian machine. However the…76 …2. The content of a vector register is the same *as if* it had been loaded with an ``LD1`` instruc…78 Because ``LD1 == LDR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can si…109 …t one advantage over ``LD1`` and ``ST1``. ``LDR`` and ``STR`` are oblivious to the size of the ind…124 …``uint16x4_t``, which is equivalent in register content, if we passed as ``LD1`` we'd break this c…133 …LD1`` only requires it to be as aligned as the lane size. If we canonicalised on using ``LDR``, we…143 | | ``LDR`` layout | ``LD1`` layout |[all …]
22 ; DBGDAG-DAG: [[LD1:t[0-9]+]]: i8,ch = load<LD1[%tmp12]> [[ENTRYTOKEN]], [[ADDPTR]], undef:i6424 ; DBGDAG: [[LOADTOKEN:t[0-9]+]]: ch = TokenFactor [[LD2]]:1, [[LD1]]:127 ; DBGDAG-DAG: [[ST1:t[0-9]+]]: ch = store<ST1[%tmp14]> [[ST2]], [[LD1]], t{{[0-9]+}}, undef:i64
38 ; CHECK-DAG: lvx [[LD1:[0-9]+]], [[B1]], [[C0]]42 ; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[PC]]
616 ; OPTALL: [[LD1:%[a-zA-Z_0-9-]+]] = load i32, i32* [[GEP]]619 ; OPT-NEXT: [[SEXTLD1:%[a-zA-Z_0-9-]+]] = sext i32 [[LD1]] to i64623 ; DISABLE-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[LD1]], %cst
2508 ### LD1 ### subsection2517 ### LD1 ### subsection2528 ### LD1 ### subsection2536 ### LD1 ### subsection2546 ### LD1 ### subsection
1367 // We must do vector loads with LD1 in big-endian.1380 // We must do vector loads with LD1 in big-endian.1507 // We must use LD1 to perform vector loads in big-endian.1526 // We must use LD1 to perform vector loads in big-endian.4938 defm LD1 : SIMDLd1Multiple<"ld1">;4982 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;4983 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;4984 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;4985 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;5031 ValueType VTy, ValueType STy, Instruction LD1>[all …]
8447 // LD1 instructions have extra "1d" variants.
7220 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); in CombineConsecutiveLoads() local7222 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || in CombineConsecutiveLoads()7223 LD1->getAddressSpace() != LD2->getAddressSpace()) in CombineConsecutiveLoads()7225 EVT LD1VT = LD1->getValueType(0); in CombineConsecutiveLoads()7231 !LD1->isVolatile() && in CombineConsecutiveLoads()7233 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { in CombineConsecutiveLoads()7234 unsigned Align = LD1->getAlignment(); in CombineConsecutiveLoads()7240 return DAG.getLoad(VT, SDLoc(N), LD1->getChain(), in CombineConsecutiveLoads()7241 LD1->getBasePtr(), LD1->getPointerInfo(), in CombineConsecutiveLoads()
843 def LD1 : WInst<"vld1", "dc", "dQdPlQPl">;
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