Searched refs:LWL (Results 1 – 17 of 17) sorted by relevance
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 221 case Mips::LWL: in isBasePlusOffsetMemoryAccess()
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| /external/v8/src/mips/ |
| D | constants-mips.h | 361 LWL = ((4U << 3) + 2) << kOpcodeShift, enumerator
900 OpcodeToBitNumber(LB) | OpcodeToBitNumber(LH) | OpcodeToBitNumber(LWL) |
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| D | disasm-mips.cc | 1563 case LWL: in DecodeTypeImmediate()
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| D | assembler-mips.cc | 1783 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_); in lwl()
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| D | simulator-mips.cc | 4209 case LWL: { in DecodeTypeImmediate()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 349 LWL = ((4U << 3) + 2) << kOpcodeShift, enumerator
947 OpcodeToBitNumber(LWL) | OpcodeToBitNumber(LW) | OpcodeToBitNumber(LWU) |
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| D | disasm-mips64.cc | 1786 case LWL: in DecodeTypeImmediate()
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| D | assembler-mips64.cc | 1994 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_); in lwl()
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| D | simulator-mips64.cc | 4438 case LWL: { in DecodeTypeImmediate()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.h | 202 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, enumerator
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| D | MipsISelLowering.cpp | 147 case MipsISD::LWL: return "MipsISD::LWL"; in getTargetNodeName()
2213 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, in lowerLOAD() local
2215 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, in lowerLOAD()
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| D | MipsInstrInfo.td | 132 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
1423 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
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| /external/valgrind/none/tests/mips32/ |
| D | MIPS32int.stdout.exp-mips32-BE | 258 LWL
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| D | MIPS32int.stdout.exp-mips32-LE | 258 LWL
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| D | MIPS32int.stdout.exp-mips32r2-LE | 644 LWL
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| D | MIPS32int.stdout.exp-mips32r2-BE | 644 LWL
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3163 emitRRI(Mips::LWL, DstRegOp.getReg(), FinalSrcReg, LeftLoadOffset, IDLoc, in expandUlw()
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