| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedA57WriteRes.td | 15 // Latency: #cyc
26 def A57Write_5cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 5; }
27 def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
28 def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
29 def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
30 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
31 def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18;
33 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
35 def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }
36 def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; }
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| D | AArch64SchedA53.td | 57 def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 3; }
58 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
59 def : WriteRes<WriteISReg, [A53UnitALU]> { let Latency = 3; }
60 def : WriteRes<WriteIEReg, [A53UnitALU]> { let Latency = 3; }
61 def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 2; }
62 def : WriteRes<WriteExtr, [A53UnitALU]> { let Latency = 3; }
65 def : WriteRes<WriteIM32, [A53UnitMAC]> { let Latency = 4; }
66 def : WriteRes<WriteIM64, [A53UnitMAC]> { let Latency = 4; }
69 def : WriteRes<WriteID32, [A53UnitDiv]> { let Latency = 4; }
70 def : WriteRes<WriteID64, [A53UnitDiv]> { let Latency = 4; }
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| D | AArch64SchedCyclone.td | 104 def WriteX : SchedWriteRes<[]> { let Latency = 0; }
155 let Latency = 2;
163 let Latency = 2;
175 let Latency = 2;
191 let Latency = 4;
195 let Latency = 5;
206 let Latency = 10;
213 let Latency = 13;
223 let Latency = 4;
233 let Latency = 4;
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| D | AArch64SchedA57.td | 78 def : WriteRes<WriteIM32, [A57UnitM]> { let Latency = 3; }
79 def : WriteRes<WriteIM64, [A57UnitM]> { let Latency = 5; }
99 def : WriteRes<WriteSys, []> { let Latency = 1; }
100 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
101 def : WriteRes<WriteHint, []> { let Latency = 1; }
103 def : WriteRes<WriteLDHi, []> { let Latency = 4; }
379 def A57WriteIVMA : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
390 def A57WriteIVA : SchedWriteRes<[A57UnitX]> { let Latency = 4; }
476 def A57WriteFPVMAD : SchedWriteRes<[A57UnitV]> { let Latency = 9; }
477 def A57WriteFPVMAQ : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 10; }
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCScheduleE5500.td | 53 [5, 2, 2], // Latency = 1
58 [5, 2, 2], // Latency = 1
63 [5, 2, 2, 2], // Latency = 1
69 [6, 2, 2], // Latency = 1 or 2
75 [30, 2, 2], // Latency= 4..26, Repeat rate= 4..26
81 [20, 2, 2], // Latency= 4..16, Repeat rate= 4..16
86 [11], // Latency = 7, Repeat rate = 1
90 [11, 2, 2], // Latency = 7, Repeat rate = 7
95 [9, 2, 2], // Latency = 4..7, Repeat rate = 2..4
101 [8, 2, 2], // Latency = 4, Repeat rate = 1
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| D | PPCScheduleE500mc.td | 49 [4, 1, 1], // Latency = 1
54 [4, 1, 1], // Latency = 1
59 [4, 1, 1, 1], // Latency = 1
65 [5, 1, 1], // Latency = 1 or 2
71 [17, 1, 1], // Latency=4..35, Repeat= 4..35
76 [11], // Latency = 8
80 [11, 1, 1], // Latency = 8
84 [7, 1, 1], // Latency = 4, Repeat rate = 1
89 [7, 1, 1], // Latency = 4, Repeat rate = 1
94 [7, 1, 1], // Latency = 4, Repeat rate = 1
[all …]
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| D | PPCInstrInfo.cpp | 123 unsigned Latency = 1; in getInstrLatency() local
134 Latency = std::max(Latency, (unsigned) Cycle); in getInstrLatency()
137 return Latency; in getInstrLatency()
144 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx, in getOperandLatency() local
148 return Latency; in getOperandLatency()
165 if (Latency < 0) in getOperandLatency()
166 Latency = getInstrLatency(ItinData, DefMI); in getOperandLatency()
184 Latency += 2; in getOperandLatency()
189 return Latency; in getOperandLatency()
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| /external/llvm/lib/Target/X86/ |
| D | X86ScheduleBtVer2.td | 12 // Optimization Guide for AMD Family 16h Processors & Instruction Latency appendix.
81 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
86 let Latency = !add(Lat, 3);
94 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
99 let Latency = !add(Lat, 5);
114 let Latency = 6;
120 let Latency = 25;
124 let Latency = 41;
143 def : WriteRes<WriteLoad, [JLAGU]> { let Latency = 5; }
178 let Latency = 21;
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| D | X86ScheduleSLM.td | 63 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
68 let Latency = !add(Lat, 3);
77 def : WriteRes<WriteLoad, [MEC_RSV]> { let Latency = 3; }
93 let Latency = 25;
97 let Latency = 29;
114 let Latency = 5;
118 let Latency = 8;
123 let Latency = 34;
127 let Latency = 37;
143 let Latency = 13;
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| D | X86SchedSandyBridge.td | 76 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
81 let Latency = !add(Lat, 4);
90 def : WriteRes<WriteLoad, [SBPort23]> { let Latency = 4; }
96 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
107 let Latency = 25;
111 let Latency = 29;
128 let Latency = 2;
132 let Latency = 6;
144 let Latency = 2;
148 let Latency = 6;
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| D | X86SchedHaswell.td | 86 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
91 let Latency = !add(Lat, 4);
102 def : WriteRes<WriteLoad, [HWPort23]> { let Latency = 4; }
108 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
119 let Latency = 25;
123 let Latency = 29;
142 let Latency = 2;
146 let Latency = 6;
160 let Latency = 2;
164 let Latency = 6;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsScheduleP5600.td | 53 let Latency = 2;
65 let Latency = 4;
69 let Latency = 4;
81 let Latency = 2;
86 let Latency = 0;
109 let Latency = 0;
116 def P5600WriteAL2BitExt : SchedWriteRes<[P5600IssueAL2]> { let Latency = 2; }
117 def P5600WriteAL2ShadowMov : SchedWriteRes<[P5600IssueAL2]> { let Latency = 2; }
119 let Latency = 2;
123 let Latency = 34;
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| /external/llvm/lib/MC/MCDisassembler/ |
| D | Disassembler.cpp | 169 int Latency = 0; in getItineraryLatency() local
172 Latency = std::max(Latency, IID.getOperandCycle(SCClass, OpIdx)); in getItineraryLatency()
174 return Latency; in getItineraryLatency()
202 int Latency = 0; in getLatency() local
208 Latency = std::max(Latency, WLEntry->Cycles); in getLatency()
211 return Latency; in getLatency()
218 int Latency = getLatency(DC, Inst); in emitLatency() local
221 if (Latency < 2) in emitLatency()
224 DC->CommentStream << "Latency: " << Latency << '\n'; in emitLatency()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 63 def SwiftWriteP0TwoCycle : SchedWriteRes<[SwiftUnitP0]> { let Latency = 2; }
64 def SwiftWriteP0FourCycle : SchedWriteRes<[SwiftUnitP0]> { let Latency = 4; }
65 def SwiftWriteP0SixCycle : SchedWriteRes<[SwiftUnitP0]> { let Latency = 6; }
67 let Latency = 4;
70 let Latency = 6;
73 def SwiftWriteP1TwoCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 2; }
74 def SwiftWriteP1FourCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 4; }
75 def SwiftWriteP1SixCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 6; }
76 def SwiftWriteP1EightCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 8; }
77 def SwiftWriteP1TwelveCyc : SchedWriteRes<[SwiftUnitP1]> { let Latency = 12; }
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| D | ARMScheduleA9.td | 1926 def A9WriteIssue : SchedWriteRes<[]> { let Latency = 0; }
1931 def A9WriteIsr : SchedWriteRes<[A9UnitALU]> { let Latency = 2; }
1936 def : WriteRes<WriteALUsi, [A9UnitALU]> { let Latency = 2; }
1938 def A9WriteALUsr : SchedWriteRes<[A9UnitALU]> { let Latency = 3; }
1941 def A9WriteM : SchedWriteRes<[A9UnitMul, A9UnitMul]> { let Latency = 4; }
1942 def A9WriteMHi : SchedWriteRes<[A9UnitMul]> { let Latency = 5;
1944 def A9WriteM16 : SchedWriteRes<[A9UnitMul]> { let Latency = 3; }
1945 def A9WriteM16Hi : SchedWriteRes<[A9UnitMul]> { let Latency = 4;
1951 def A9WriteF : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 4; }
1952 def A9WriteFMov : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 1; }
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| D | ARMBaseInstrInfo.cpp | 3690 unsigned Latency = getInstrLatency(ItinData, DefMI); in getOperandLatency() local
3696 if (Latency > 0 && Subtarget.isThumb2()) { in getOperandLatency()
3700 --Latency; in getOperandLatency()
3702 return Latency; in getOperandLatency()
3714 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign, in getOperandLatency() local
3717 if (Latency < 0) in getOperandLatency()
3718 return Latency; in getOperandLatency()
3725 if (Adj >= 0 || (int)Latency > -Adj) { in getOperandLatency()
3726 return Latency + Adj; in getOperandLatency()
3729 return Latency; in getOperandLatency()
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| D | ARMSchedule.td | 19 // Uops | Latency from register | Uops - resource requirements - latency
49 // Latency = 4; // Latency of 4.
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| /external/llvm/lib/CodeGen/ |
| D | TargetSchedule.cpp | 194 unsigned Latency = capLatency(WLEntry->Cycles); in computeOperandLatency() local
196 return Latency; in computeOperandLatency()
201 return Latency; in computeOperandLatency()
204 if (Advance > 0 && (unsigned)Advance > Latency) // unsigned wrap in computeOperandLatency()
206 return Latency - Advance; in computeOperandLatency()
227 unsigned Latency = 0; in computeInstrLatency() local
233 Latency = std::max(Latency, capLatency(WLEntry->Cycles)); in computeInstrLatency()
235 return Latency; in computeInstrLatency()
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| D | CriticalAntiDepBreaker.cpp | 442 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency) in BreakAntiDependencies()
449 << (Max->getDepth() + Max->Latency) << "\n"); in BreakAntiDependencies()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAG.h | 92 unsigned Latency; variable
111 Latency = 0; in SDep()
115 Latency = 1; in SDep()
120 : Dep(S, Order), Contents(), Latency(0) { in SDep()
139 return overlaps(Other) && Latency == Other.Latency;
151 return Latency; in getLatency()
156 Latency = Lat; in setLatency()
292 unsigned short Latency; // Node latency.
329 NumRegDefsLeft(0), Latency(0), isVRegCycle(false), isCall(false),
345 NumRegDefsLeft(0), Latency(0), isVRegCycle(false), isCall(false),
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| /external/llvm/test/CodeGen/ARM/ |
| D | 2012-06-12-SchedMemLatency.ll | 10 ; CHECK: ch SU(3): Latency=1
14 ; CHECK: ch SU(2): Latency=1
20 ; CHECK: ch SU(3): Latency=1
24 ; CHECK: ch SU(2): Latency=1
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrItineraries.h | 158 unsigned Latency = 0, StartCycle = 0; in getStageLatency() local
161 Latency = std::max(Latency, StartCycle + IS->getCycles()); in getStageLatency()
164 return Latency; in getStageLatency()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.cpp | 92 SU->Latency = Old->Latency; in Clone()
481 unsigned OpLatency = isChain ? 1 : OpSU->Latency; in AddSchedEdges()
598 SU->Latency = 0; in computeLatency()
604 SU->Latency = 1; in computeLatency()
611 SU->Latency = HighLatencyCycles; in computeLatency()
613 SU->Latency = 1; in computeLatency()
619 SU->Latency = 0; in computeLatency()
622 SU->Latency += TII->getInstrLatency(InstrItins, N); in computeLatency()
638 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in computeOperandLatency() local
639 if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg && in computeOperandLatency()
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| /external/webrtc/webrtc/test/channel_transport/ |
| D | udp_socket2_win.cc | 729 Qos.SendingFlowspec.Latency = QOS_NOT_SPECIFIED; in SetQos()
738 Qos.ReceivingFlowspec.Latency = QOS_NOT_SPECIFIED; in SetQos()
1039 _flow->SendingFlowspec.Latency = QOS_NOT_SPECIFIED; in SetTrafficControl()
1048 _flow->ReceivingFlowspec.Latency = QOS_NOT_SPECIFIED; in SetTrafficControl()
1108 _flow->SendingFlowspec.Latency = QOS_NOT_SPECIFIED; in SetTrafficControl()
1122 _flow->SendingFlowspec.Latency = send->Latency; in SetTrafficControl()
1137 _flow->ReceivingFlowspec.Latency = _flow->SendingFlowspec.Latency; in SetTrafficControl()
1151 _flow->ReceivingFlowspec.Latency = recv->Latency; in SetTrafficControl()
1251 f->Latency = QOS_NOT_SPECIFIED; in CreateFlowSpec()
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-misched-forwarding-A53.ll | 11 ; CHECK-NEXT: val SU(4): Latency=1 Reg=%vreg2
12 ; CHECK-NEXT: val SU(3): Latency=2 Reg=%vreg2
|