Searched refs:MTC1 (Results 1 – 15 of 15) sorted by relevance
/external/llvm/lib/Target/Mips/ |
D | MipsSEInstrInfo.cpp | 118 Opc = Mips::MTC1; in copyPhysReg() 366 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); in expandPostRAPseudo() 369 expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false); in expandPostRAPseudo() 375 expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true); in expandPostRAPseudo() 630 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); in expandBuildPairF64()
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D | MipsInstrFPU.td | 368 def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, 569 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>; 570 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
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D | MipsAsmPrinter.cpp | 799 if (Opcode == Mips::MTC1) { in EmitInstrRegReg() 838 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1; in EmitSwapFPIntParams()
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D | MipsFastISel.cpp | 336 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
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/external/v8/src/mips/ |
D | constants-mips.h | 485 MTC1 = ((0U << 3) + 4) << 21, enumerator
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D | disasm-mips.cc | 1307 case MTC1: in DecodeTypeRegister()
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D | assembler-mips.cc | 2175 GenInstrRegister(COP1, MTC1, rt, fs, f0); in mtc1()
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D | simulator-mips.cc | 3396 case MTC1: in DecodeTypeRegisterCOP1()
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/external/pcre/dist/sljit/ |
D | sljitNativeMIPS_common.c | 151 #define MTC1 (HI(17) | (4 << 21)) macro 1338 FAIL_IF(push_inst(compiler, MTC1 | flags | T(src) | FS(TMP_FREG1), MOVABLE_INS)); in sljit_emit_fop1_convd_fromw() 1349 FAIL_IF(push_inst(compiler, MTC1 | flags | T(TMP_REG1) | FS(TMP_FREG1), MOVABLE_INS)); in sljit_emit_fop1_convd_fromw()
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/external/v8/src/mips64/ |
D | constants-mips64.h | 527 MTC1 = ((0U << 3) + 4) << 21, enumerator
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D | disasm-mips64.cc | 1085 case MTC1: in DecodeTypeRegisterCOP1()
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D | assembler-mips64.cc | 2528 GenInstrRegister(COP1, MTC1, rt, fs, f0); in mtc1()
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D | simulator-mips64.cc | 3334 case MTC1: in DecodeTypeRegisterCOP1()
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/external/valgrind/none/tests/mips32/ |
D | MoveIns.stdout.exp-BE | 29 MTC1
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D | MoveIns.stdout.exp | 29 MTC1
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