| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.h | 46 unsigned isLoadFromStackSlot(const MachineInstr *MI,
54 unsigned isStoreToStackSlot(const MachineInstr *MI,
186 bool isPredicated(const MachineInstr *MI) const override;
190 bool PredicateInstruction(MachineInstr *MI,
201 bool DefinesPredicate(MachineInstr *MI,
207 bool isPredicable(MachineInstr *MI) const override;
211 bool isSchedulingBoundary(const MachineInstr *MI,
230 bool analyzeCompare(const MachineInstr *MI,
238 const MachineInstr *MI,
249 bool areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
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| D | HexagonVLIWPacketizer.h | 12 std::vector<MachineInstr*> OldPacketMIs;
32 std::vector<MachineInstr*> IgnoreDepMIs;
53 bool ignorePseudoInstruction(const MachineInstr *MI,
58 bool isSoloInstruction(const MachineInstr *MI) override;
68 MachineBasicBlock::iterator addToPacket(MachineInstr *MI) override;
69 void endPacket(MachineBasicBlock *MBB, MachineInstr *MI) override;
70 bool shouldAddToPacket(const MachineInstr *MI) override;
75 bool isCallDependent(const MachineInstr* MI, SDep::Kind DepType,
77 bool promoteToDotCur(MachineInstr* MI, SDep::Kind DepType,
80 bool canPromoteToDotCur(const MachineInstr* MI, const SUnit* PacketSU,
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| D | HexagonVLIWPacketizer.cpp | 112 static bool hasWriteToReadDep(const MachineInstr *FirstI, in hasWriteToReadDep()
113 const MachineInstr *SecondI, const TargetRegisterInfo *TRI) { in hasWriteToReadDep()
125 static MachineBasicBlock::iterator moveInstrOut(MachineInstr *MI, in moveInstrOut()
138 MI->clearFlag(MachineInstr::BundledSucc); in moveInstrOut()
139 MI->clearFlag(MachineInstr::BundledPred); in moveInstrOut()
162 MachineInstr *SingleI = BundleIt->getNextNode(); in moveInstrOut()
265 bool HexagonPacketizerList::isCallDependent(const MachineInstr* MI, in isCallDependent()
295 static bool isDirectJump(const MachineInstr* MI) { in isDirectJump()
299 static bool isSchedBarrier(const MachineInstr* MI) { in isSchedBarrier()
307 static bool isControlFlow(const MachineInstr* MI) { in isControlFlow()
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 81 bool isTriviallyReMaterializable(const MachineInstr *MI,
97 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, in isReallyTriviallyReMaterializable()
117 virtual MachineInstr *commuteInstructionImpl(MachineInstr *MI,
142 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
160 virtual int getSPAdjust(const MachineInstr *MI) const;
167 virtual bool isCoalescableExtInstr(const MachineInstr &MI, in isCoalescableExtInstr()
178 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, in isLoadFromStackSlot()
185 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, in isLoadFromStackSlotPostFE()
196 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
205 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, in isStoreToStackSlot()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 44 void lowerScalarAbs(SmallVectorImpl<MachineInstr *> &Worklist,
45 MachineInstr *Inst) const;
47 void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
48 MachineInstr *Inst, unsigned Opcode) const;
50 void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
51 MachineInstr *Inst, unsigned Opcode) const;
53 void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
54 MachineInstr *Inst) const;
55 void splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
56 MachineInstr *Inst) const;
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| D | R600InstrInfo.h | 29 class MachineInstr; variable
37 ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const;
71 bool isTrig(const MachineInstr &MI) const;
85 bool canBeConsideredALU(const MachineInstr *MI) const;
88 bool isTransOnly(const MachineInstr *MI) const;
90 bool isVectorOnly(const MachineInstr *MI) const;
94 bool usesVertexCache(const MachineInstr *MI) const;
96 bool usesTextureCache(const MachineInstr *MI) const;
99 bool usesAddressRegister(MachineInstr *MI) const;
100 bool definesAddressRegister(MachineInstr *MI) const;
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| D | AMDGPUInstrInfo.h | 37 class MachineInstr; variable
51 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
54 unsigned isLoadFromStackSlot(const MachineInstr *MI,
56 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
58 bool hasLoadFromStackSlot(const MachineInstr *MI,
61 unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
62 unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI,
64 bool hasStoreFromStackSlot(const MachineInstr *MI,
68 MachineInstr *
88 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 123 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { in isLeaMem()
135 inline static bool isMem(const MachineInstr *MI, unsigned Op) { in isMem()
173 SmallVectorImpl<MachineInstr *> &CondBranches,
188 int getSPAdjust(const MachineInstr *MI) const override;
196 bool isCoalescableExtInstr(const MachineInstr &MI,
200 unsigned isLoadFromStackSlot(const MachineInstr *MI,
205 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
208 unsigned isStoreToStackSlot(const MachineInstr *MI,
213 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
216 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
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| D | X86OptimizeLEAs.cpp | 57 int calcInstrDist(const MachineInstr &First, const MachineInstr &Last);
63 bool chooseBestLEA(const SmallVectorImpl<MachineInstr *> &List,
64 const MachineInstr &MI, MachineInstr *&LEA,
72 bool isLEA(const MachineInstr &MI);
78 bool isSimilarMemOp(const MachineInstr &MI1, unsigned N1,
79 const MachineInstr &MI2, unsigned N2,
84 SmallVectorImpl<MachineInstr *> &List);
87 bool removeRedundantAddrCalc(const SmallVectorImpl<MachineInstr *> &List);
100 int OptimizeLEAPass::calcInstrDist(const MachineInstr &First, in calcInstrDist()
101 const MachineInstr &Last) { in calcInstrDist()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstrInfo.h | 37 class MachineInstr; variable
51 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
54 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
55 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
57 bool hasLoadFromStackSlot(const MachineInstr *MI,
60 unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
61 unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI,
63 bool hasStoreFromStackSlot(const MachineInstr *MI,
67 MachineInstr *
90 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
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| D | AMDGPUInstrInfo.cpp | 36 bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, in isCoalescableExtInstr()
43 unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, in isLoadFromStackSlot()
49 unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, in isLoadFromStackSlotPostFE()
55 bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, in hasLoadFromStackSlot()
61 unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI, in isStoreFromStackSlot()
66 unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI, in isStoreFromStackSlotPostFE()
71 bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI, in hasStoreFromStackSlot()
78 MachineInstr *
140 MachineInstr *
142 MachineInstr *MI, in foldMemoryOperandImpl()
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| D | R600InstrInfo.h | 29 class MachineInstr; variable
48 bool isTrig(const MachineInstr &MI) const;
55 bool isVector(const MachineInstr &MI) const;
57 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
75 bool isPredicated(const MachineInstr *MI) const;
77 bool isPredicable(MachineInstr *MI) const;
94 bool DefinesPredicate(MachineInstr *MI,
103 bool PredicateInstruction(MachineInstr *MI,
107 const MachineInstr *MI,
115 bool hasFlagOperand(const MachineInstr &MI) const;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.h | 48 unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
50 bool isAsCheapAsAMove(const MachineInstr *MI) const override;
52 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
56 areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
59 unsigned isLoadFromStackSlot(const MachineInstr *MI,
61 unsigned isStoreToStackSlot(const MachineInstr *MI,
66 bool hasShiftedReg(const MachineInstr *MI) const;
70 bool hasExtendedReg(const MachineInstr *MI) const;
73 bool isGPRZero(const MachineInstr *MI) const;
76 bool isGPRCopy(const MachineInstr *MI) const;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 56 const MachineInstr &MI, unsigned DefIdx,
69 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
85 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
96 MachineInstr *commuteInstructionImpl(MachineInstr *MI,
109 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
138 bool isPredicated(const MachineInstr *MI) const override;
140 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const { in getPredicate()
146 bool PredicateInstruction(MachineInstr *MI,
152 bool DefinesPredicate(MachineInstr *MI,
155 bool isPredicable(MachineInstr *MI) const override;
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| D | MLxExpansionPass.cpp | 58 MachineInstr* LastMIs[4];
59 SmallPtrSet<MachineInstr*, 4> IgnoreStall;
62 void pushStack(MachineInstr *MI);
63 MachineInstr *getAccDefMI(MachineInstr *MI) const;
64 unsigned getDefReg(MachineInstr *MI) const;
65 bool hasLoopHazard(MachineInstr *MI) const;
66 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
67 bool FindMLxHazard(MachineInstr *MI);
68 void ExpandFPMLxInstruction(MachineBasicBlock &MBB, MachineInstr *MI,
81 void MLxExpansion::pushStack(MachineInstr *MI) { in pushStack()
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| D | A15SDOptimizer.cpp | 64 bool runOnInstruction(MachineInstr *MI);
104 bool hasPartialWrite(MachineInstr *MI);
105 SmallVector<unsigned, 8> getReadDPRs(MachineInstr *MI);
112 MachineInstr *elideCopies(MachineInstr *MI);
113 void elideCopiesAndPHIs(MachineInstr *MI,
114 SmallVectorImpl<MachineInstr*> &Outs);
119 unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg);
120 unsigned optimizeSDPattern(MachineInstr *MI);
126 void eraseInstrWithNoUses(MachineInstr *MI);
131 std::map<MachineInstr*, unsigned> Replacements;
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| /external/llvm/include/llvm/CodeGen/ |
| D | LiveVariables.h | 89 std::vector<MachineInstr*> Kills;
94 bool removeKill(MachineInstr *MI) { in removeKill()
95 std::vector<MachineInstr*>::iterator in removeKill()
104 MachineInstr *findKill(const MachineBasicBlock *MBB) const;
137 std::vector<MachineInstr *> PhysRegDef;
142 std::vector<MachineInstr *> PhysRegUse;
148 DenseMap<MachineInstr*, unsigned> DistanceMap;
153 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
158 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
159 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
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| D | MachineInstrBundle.h | 46 inline MachineInstr *getBundleStart(MachineInstr *MI) { in getBundleStart()
53 inline const MachineInstr *getBundleStart(const MachineInstr *MI) { in getBundleStart()
62 getBundleEnd(MachineInstr *MI) { in getBundleEnd()
71 getBundleEnd(const MachineInstr *MI) { in getBundleEnd()
96 MachineInstr::mop_iterator OpI, OpE;
117 explicit MachineOperandIteratorBase(MachineInstr *MI, bool WholeBundle) { in MachineOperandIteratorBase()
204 SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops = nullptr);
219 MIOperands(MachineInstr *MI) : MachineOperandIteratorBase(MI, false) {} in MIOperands()
228 ConstMIOperands(const MachineInstr *MI) in ConstMIOperands()
229 : MachineOperandIteratorBase(const_cast<MachineInstr*>(MI), false) {} in ConstMIOperands()
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| D | MachineBasicBlock.h | 40 struct ilist_traits<MachineInstr> : public ilist_default_traits<MachineInstr> {
42 mutable ilist_half_node<MachineInstr> Sentinel;
49 MachineInstr *createSentinel() const {
50 return static_cast<MachineInstr*>(&Sentinel);
52 void destroySentinel(MachineInstr *) const {}
54 MachineInstr *provideInitialHead() const { return createSentinel(); }
55 MachineInstr *ensureHead(MachineInstr*) const { return createSentinel(); }
56 static void noteHead(MachineInstr*, MachineInstr*) {}
58 void addNodeToList(MachineInstr* N);
59 void removeNodeFromList(MachineInstr* N);
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 74 SmallVectorImpl<MachineInstr*> &NewMIs,
79 SmallVectorImpl<MachineInstr*> &NewMIs,
94 MachineInstr *commuteInstructionImpl(MachineInstr *MI,
116 const MachineInstr *MI,
120 const MachineInstr *DefMI, unsigned DefIdx,
121 const MachineInstr *UseMI,
131 const MachineInstr *DefMI, in hasLowDefLatency()
147 MachineInstr &Root,
150 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
152 bool isCoalescableExtInstr(const MachineInstr &MI,
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.h | 123 void expandRIPseudo(MachineInstr *MI, unsigned LowOpcode,
125 void expandRIEPseudo(MachineInstr *MI, unsigned LowOpcode,
127 void expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode,
129 void expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode,
140 unsigned isLoadFromStackSlot(const MachineInstr *MI,
142 unsigned isStoreToStackSlot(const MachineInstr *MI,
144 bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
154 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
156 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
159 bool isPredicable(MachineInstr *MI) const override;
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| D | SystemZElimCompare.cpp | 70 Reference getRegReferences(MachineInstr *MI, unsigned Reg);
71 bool convertToBRCT(MachineInstr *MI, MachineInstr *Compare,
72 SmallVectorImpl<MachineInstr *> &CCUsers);
73 bool convertToLoadAndTest(MachineInstr *MI);
74 bool adjustCCMasksForInstr(MachineInstr *MI, MachineInstr *Compare,
75 SmallVectorImpl<MachineInstr *> &CCUsers);
76 bool optimizeCompareZero(MachineInstr *Compare,
77 SmallVectorImpl<MachineInstr *> &CCUsers);
78 bool fuseCompareAndBranch(MachineInstr *Compare,
79 SmallVectorImpl<MachineInstr *> &CCUsers);
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.h | 27 class MachineInstr; variable
36 void EmitInstrWithMacroNoAT(const MachineInstr *MI);
41 const MachineInstr *MI);
47 const MachineInstr *MI);
120 void EmitInstruction(const MachineInstr *MI) override;
130 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
133 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
136 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
137 void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O);
138 void printUnsignedImm8(const MachineInstr *MI, int opNum, raw_ostream &O);
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| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 151 bool optimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB);
152 bool optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
153 SmallPtrSetImpl<MachineInstr*> &LocalMIs);
154 bool optimizeSelect(MachineInstr *MI,
155 SmallPtrSetImpl<MachineInstr *> &LocalMIs);
156 bool optimizeCondBranch(MachineInstr *MI);
157 bool optimizeCoalescableCopy(MachineInstr *MI);
158 bool optimizeUncoalescableCopy(MachineInstr *MI,
159 SmallPtrSetImpl<MachineInstr *> &LocalMIs);
162 bool isMoveImmediate(MachineInstr *MI,
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| D | MachineLICM.cpp | 111 DenseMap<unsigned, std::vector<const MachineInstr*> > CSEMap;
158 MachineInstr *MI;
161 CandidateInfo(MachineInstr *mi, unsigned def, int fi) in CandidateInfo()
167 void HoistPostRA(MachineInstr *MI, unsigned Def);
169 void ProcessMI(MachineInstr *MI, BitVector &PhysRegDefs,
175 bool IsLICMCandidate(MachineInstr &I);
177 bool IsLoopInvariantInst(MachineInstr &I);
179 bool HasLoopPHIUse(const MachineInstr *MI) const;
181 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
184 bool IsCheapInstruction(MachineInstr &MI) const;
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