Home
last modified time | relevance | path

Searched refs:NumVecs (Results 1 – 5 of 5) sorted by relevance

/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp212 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
220 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
228 bool isUpdating, unsigned NumVecs,
234 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
240 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
272 SDValue GetVLDSTAlign(SDValue Align, SDLoc dl, unsigned NumVecs,
1684 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1685 unsigned NumRegs = NumVecs; in GetVLDSTAlign()
1686 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
1804 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLD() argument
[all …]
DARMISelLowering.cpp9514 unsigned NumVecs = 0; in CombineBaseUpdate() local
9520 NumVecs = 1; break; in CombineBaseUpdate()
9522 NumVecs = 2; break; in CombineBaseUpdate()
9524 NumVecs = 3; break; in CombineBaseUpdate()
9526 NumVecs = 4; break; in CombineBaseUpdate()
9528 NumVecs = 2; isLaneOp = true; break; in CombineBaseUpdate()
9530 NumVecs = 3; isLaneOp = true; break; in CombineBaseUpdate()
9532 NumVecs = 4; isLaneOp = true; break; in CombineBaseUpdate()
9534 NumVecs = 1; isLoadOp = false; break; in CombineBaseUpdate()
9536 NumVecs = 2; isLoadOp = false; break; in CombineBaseUpdate()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp150 SDNode *SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
154 SDNode *SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
156 SDNode *SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
158 SDNode *SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
159 SDNode *SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
161 SDNode *SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
162 SDNode *SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
163 SDNode *SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
164 SDNode *SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
1018 SDNode *AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, in SelectTable() argument
[all …]
DAArch64ISelLowering.cpp9078 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
9083 NumVecs = 2; break; in performNEONPostLDSTCombine()
9085 NumVecs = 3; break; in performNEONPostLDSTCombine()
9087 NumVecs = 4; break; in performNEONPostLDSTCombine()
9089 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
9091 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
9093 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
9095 NumVecs = 2; break; in performNEONPostLDSTCombine()
9097 NumVecs = 3; break; in performNEONPostLDSTCombine()
9099 NumVecs = 4; break; in performNEONPostLDSTCombine()
[all …]
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp27079 unsigned NumVecs = VT.getSizeInBits() / 128; in PerformSExtCombine() local
27085 for (unsigned i = 0, Offset = 0; i != NumVecs; in PerformSExtCombine()