| /external/llvm/utils/TableGen/ |
| D | X86RecognizableInstr.h | 52 uint8_t OpSize; variable
125 bool hasREX_WPrefix, uint8_t OpSize);
136 uint8_t OpSize);
141 uint8_t OpSize);
146 uint8_t OpSize);
148 uint8_t OpSize);
150 uint8_t OpSize);
152 uint8_t OpSize);
154 uint8_t OpSize);
156 uint8_t OpSize);
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| D | X86RecognizableInstr.cpp | 211 OpSize = byteFromRec(Rec, "OpSizeBits"); in RecognizableInstr()
420 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) in insnContext()
424 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) in insnContext()
426 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) in insnContext()
428 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) in insnContext()
430 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) in insnContext()
447 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) in insnContext()
449 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) in insnContext()
451 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) in insnContext()
453 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) in insnContext()
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| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | SIMCCodeEmitter.cpp | 44 uint32_t getLitEncoding(const MCOperand &MO, unsigned OpSize) const;
164 unsigned OpSize) const { in getLitEncoding()
173 if (OpSize == 4) in getLitEncoding()
176 assert(OpSize == 8); in getLitEncoding()
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| /external/llvm/lib/IR/ |
| D | Metadata.cpp | 393 size_t OpSize = NumOps * sizeof(MDOperand); in operator new() local
396 OpSize = RoundUpToAlignment(OpSize, llvm::alignOf<uint64_t>()); in operator new()
397 void *Ptr = reinterpret_cast<char *>(::operator new(OpSize + Size)) + OpSize; in operator new()
406 size_t OpSize = N->NumOperands * sizeof(MDOperand); in operator delete() local
407 OpSize = RoundUpToAlignment(OpSize, llvm::alignOf<uint64_t>()); in operator delete()
412 ::operator delete(reinterpret_cast<char *>(Mem) - OpSize); in operator delete()
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| /external/llvm/test/CodeGen/X86/ |
| D | rotate4.ll | 4 ; a << (b & (OpSize-1)) | a >> ((0 - b) & (OpSize-1))
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| /external/llvm/include/llvm/Analysis/ |
| D | TargetTransformInfoImpl.h | 76 unsigned OpSize = OpTy->getScalarSizeInBits(); in getOperationCost() local
77 if (DL.isLegalInteger(OpSize) && in getOperationCost()
78 OpSize <= DL.getPointerTypeSizeInBits(Ty)) in getOperationCost()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 307 bool isInlineConstant(const MachineOperand &MO, unsigned OpSize) const;
308 bool isLiteralConstant(const MachineOperand &MO, unsigned OpSize) const;
320 unsigned OpSize) const;
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| D | SIFoldOperands.cpp | 321 unsigned OpSize = TII->getOpSize(MI, 1); in runOnMachineFunction() local
333 if (FoldingImm && !TII->isInlineConstant(OpToFold, OpSize) && in runOnMachineFunction()
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| D | SIInstrInfo.cpp | 1323 unsigned OpSize) const { in isInlineConstant()
1331 unsigned BitSize = 8 * OpSize; in isInlineConstant()
1339 unsigned OpSize) const { in isLiteralConstant()
1340 return MO.isImm() && !isInlineConstant(MO, OpSize); in isLiteralConstant()
1370 unsigned OpSize = RI.getRegClass(OpInfo.RegClass)->getSize(); in isImmOperandLegal() local
1371 if (isLiteralConstant(MO, OpSize)) in isImmOperandLegal()
1401 unsigned OpSize) const { in usesConstantBus()
1403 if (isLiteralConstant(MO, OpSize)) in usesConstantBus()
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| /external/llvm/lib/Analysis/ |
| D | ConstantFolding.cpp | 662 unsigned OpSize = DL.getTypeSizeInBits(Op0->getType()); in SymbolicallyEvaluateBinop() local
667 return ConstantInt::get(Op0->getType(), Offs1.zextOrTrunc(OpSize) - in SymbolicallyEvaluateBinop()
668 Offs2.zextOrTrunc(OpSize)); in SymbolicallyEvaluateBinop()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrFormats.td | 164 class OpSize16 { OperandSize OpSize = OpSize16; }
165 class OpSize32 { OperandSize OpSize = OpSize32; }
248 OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change
250 bits<2> OpSizeBits = OpSize.Value;
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| D | X86InstrArithmetic.td | 605 /// OpSize - Selects whether the instruction needs a 0x66 prefix based on
608 OperandSize OpSize = opSize;
649 let OpSize = typeinfo.OpSize;
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| D | X86ISelLowering.cpp | 3341 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; in LowerCall() local
3342 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); in LowerCall()
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| D | X86InstrSSE.td | 2165 // SSE2 instructions without OpSize prefix
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 3044 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8 in LowerCall() local
3046 OpSize = (OpSize + 7) / 8; in LowerCall()
3049 if (OpSize < 8) in LowerCall()
3050 BEAlign = 8 - OpSize; in LowerCall()
3059 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); in LowerCall()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 13064 int OpSize = OpVT.getVectorNumElements(); in simplifyShuffleOperandRecursively() local
13065 SmallBitVector OpUsedElements(OpSize, false); in simplifyShuffleOperandRecursively()
13072 for (int j = 0; j < OpSize; ++j) in simplifyShuffleOperandRecursively()
13073 if (UsedElements[i * OpSize + j]) { in simplifyShuffleOperandRecursively()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 3975 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; in CalculateTailCallArgDest() local
3976 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); in CalculateTailCallArgDest()
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