| /external/llvm/lib/Target/Mips/ |
| D | MipsCCState.h | 38 void PreAnalyzeReturnForF128(const SmallVectorImpl<ISD::OutputArg> &Outs);
43 PreAnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
73 AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeCallOperands() argument
77 PreAnalyzeCallOperands(Outs, FuncArgs, CallNode); in AnalyzeCallOperands()
78 CCState::AnalyzeCallOperands(Outs, Fn); in AnalyzeCallOperands()
87 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
89 void AnalyzeCallOperands(const SmallVectorImpl<MVT> &Outs,
110 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeReturn() argument
112 PreAnalyzeReturnForF128(Outs); in AnalyzeReturn()
113 CCState::AnalyzeReturn(Outs, Fn); in AnalyzeReturn()
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| D | MipsCCState.cpp | 87 const SmallVectorImpl<ISD::OutputArg> &Outs) { in PreAnalyzeReturnForF128() argument
89 for (unsigned i = 0; i < Outs.size(); ++i) { in PreAnalyzeReturnForF128()
100 const SmallVectorImpl<ISD::OutputArg> &Outs, in PreAnalyzeCallOperands() argument
103 for (unsigned i = 0; i < Outs.size(); ++i) { in PreAnalyzeCallOperands()
105 originalTypeIsF128(FuncArgs[Outs[i].OrigArgIndex].Ty, CallNode)); in PreAnalyzeCallOperands()
107 FuncArgs[Outs[i].OrigArgIndex].Ty->isFloatingPointTy()); in PreAnalyzeCallOperands()
108 CallOperandIsFixed.push_back(Outs[i].IsFixed); in PreAnalyzeCallOperands()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZCallingConv.h | 58 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeCallOperands() argument
62 for (unsigned i = 0; i < Outs.size(); ++i) in AnalyzeCallOperands()
63 ArgIsFixed.push_back(Outs[i].IsFixed); in AnalyzeCallOperands()
66 for (unsigned i = 0; i < Outs.size(); ++i) in AnalyzeCallOperands()
67 ArgIsShortVector.push_back(IsShortVectorType(Outs[i].ArgVT)); in AnalyzeCallOperands()
69 CCState::AnalyzeCallOperands(Outs, Fn); in AnalyzeCallOperands()
74 void AnalyzeCallOperands(const SmallVectorImpl<MVT> &Outs,
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| D | SystemZISelLowering.h | 442 const SmallVectorImpl<ISD::OutputArg> &Outs,
445 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /external/llvm/lib/CodeGen/ |
| D | CallingConvLower.cpp | 89 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in CheckReturn() argument
92 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { in CheckReturn()
93 MVT VT = Outs[i].VT; in CheckReturn()
94 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; in CheckReturn()
103 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeReturn() argument
106 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { in AnalyzeReturn()
107 MVT VT = Outs[i].VT; in AnalyzeReturn()
108 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; in AnalyzeReturn()
121 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeCallOperands() argument
123 unsigned NumOps = Outs.size(); in AnalyzeCallOperands()
[all …]
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 346 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall() local
347 for (const ISD::OutputArg &Out : Outs) { in LowerCall()
463 const SmallVectorImpl<ISD::OutputArg> &Outs, in CanLowerReturn() argument
466 return Outs.size() <= 1; in CanLowerReturn()
471 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn() argument
474 assert(Outs.size() <= 1 && "WebAssembly can only return up to one value"); in LowerReturn()
483 for (const ISD::OutputArg &Out : Outs) { in LowerReturn()
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| D | WebAssemblyISelLowering.h | 64 const SmallVectorImpl<ISD::OutputArg> &Outs,
67 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.h | 141 const SmallVectorImpl<ISD::OutputArg> &Outs,
146 const SmallVectorImpl<ISD::OutputArg> &Outs,
151 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| D | SparcISelLowering.cpp | 196 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn() argument
200 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); in LowerReturn()
201 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); in LowerReturn()
207 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn_32() argument
220 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32); in LowerReturn_32()
292 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn_64() argument
303 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64); in LowerReturn_64()
739 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall_32() local
755 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32); in LowerCall_32()
767 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { in LowerCall_32()
[all …]
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 258 auto &Outs = CLI.Outs; in LowerCall() local
283 CCInfo.AnalyzeCallOperands(Outs, CC_BPF64); in LowerCall()
287 if (Outs.size() >= 6) { in LowerCall()
293 for (auto &Arg : Outs) { in LowerCall()
389 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn() argument
407 CCInfo.AnalyzeReturn(Outs, RetCC_BPF64); in LowerReturn()
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| D | BPFISelLowering.h | 73 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 265 const SmallVectorImpl<ISD::OutputArg> &Outs) { in AnalyzeVarArgs() argument
266 State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack); in AnalyzeVarArgs()
350 const SmallVectorImpl<ISD::OutputArg> &Outs) { in AnalyzeRetResult() argument
351 State.AnalyzeReturn(Outs, RetCC_MSP430); in AnalyzeRetResult()
394 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall() local
412 Outs, OutVals, Ins, dl, DAG, InVals); in LowerCall()
523 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn() argument
531 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) in LowerReturn()
539 AnalyzeReturnValues(CCInfo, RVLocs, Outs); in LowerReturn()
578 &Outs, in LowerCCCCallTo() argument
[all …]
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| D | MSP430ISelLowering.h | 133 const SmallVectorImpl<ISD::OutputArg> &Outs,
165 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.h | 794 const SmallVectorImpl<ISD::OutputArg> &Outs,
800 const SmallVectorImpl<ISD::OutputArg> &Outs,
836 const SmallVectorImpl<ISD::OutputArg> &Outs,
846 const SmallVectorImpl<ISD::OutputArg> &Outs,
855 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.h | 156 const SmallVectorImpl<ISD::OutputArg> &Outs,
223 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| D | XCoreISelLowering.cpp | 1048 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall() local
1068 Outs, OutVals, Ins, dl, DAG, InVals); in LowerCall()
1125 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerCCCCallTo() argument
1140 CCInfo.AnalyzeCallOperands(Outs, CC_XCore); in LowerCCCCallTo()
1454 const SmallVectorImpl<ISD::OutputArg> &Outs, in CanLowerReturn() argument
1458 if (!CCInfo.CheckReturn(Outs, RetCC_XCore)) in CanLowerReturn()
1468 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn() argument
1488 CCInfo.AnalyzeReturn(Outs, RetCC_XCore); in LowerReturn()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.h | 110 bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,
157 bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 428 const SmallVectorImpl<ISD::OutputArg> &Outs,
447 const SmallVectorImpl<ISD::OutputArg> &Outs,
451 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 300 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
311 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 616 const SmallVectorImpl<ISD::OutputArg> &Outs,
623 const SmallVectorImpl<ISD::OutputArg> &Outs,
629 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| D | A15SDOptimizer.cpp | 114 SmallVectorImpl<MachineInstr*> &Outs);
366 SmallVectorImpl<MachineInstr*> &Outs) { in elideCopiesAndPHIs() argument
400 Outs.push_back(MI); in elideCopiesAndPHIs()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FunctionLoweringInfo.cpp | 93 SmallVector<ISD::OutputArg, 4> Outs; in set() local
94 GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI, in set()
97 Fn->isVarArg(), Outs, Fn->getContext()); in set()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUISelLowering.h | 52 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 900 const SmallVectorImpl<ISD::OutputArg> &Outs, unsigned retAlignment, in getPrototype() argument
953 if (!Outs[OIdx].Flags.isByVal()) { in getPrototype()
972 assert((getValueType(DL, Ty) == Outs[OIdx].VT || in getPrototype()
973 (getValueType(DL, Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) && in getPrototype()
993 unsigned align = Outs[OIdx].Flags.getByValAlign(); in getPrototype()
1056 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall() local
1094 EVT VT = Outs[OIdx].VT; in LowerCall()
1097 if (!Outs[OIdx].Flags.isByVal()) { in LowerCall()
1301 if (Outs[OIdx].Flags.isSExt()) in LowerCall()
1312 if (Outs[OIdx].Flags.isZExt()) in LowerCall()
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 990 const SmallVectorImpl<ISD::OutputArg> &Outs,
1061 const SmallVectorImpl<ISD::OutputArg> &Outs,
1074 const SmallVectorImpl<ISD::OutputArg> &Outs,
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