1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the interface defintiion of the TargetLowering class
11 // that is common to all AMD GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef AMDGPUISELLOWERING_H
16 #define AMDGPUISELLOWERING_H
17 
18 #include "llvm/Target/TargetLowering.h"
19 
20 namespace llvm {
21 
22 class MachineRegisterInfo;
23 
24 class AMDGPUTargetLowering : public TargetLowering
25 {
26 private:
27   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
28   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
29 
30 protected:
31 
32   /// CreateLiveInRegister - Helper function that adds Reg to the LiveIn list
33   /// of the DAG's MachineFunction.  This returns a Register SDNode representing
34   /// Reg.
35   SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
36                                                   unsigned Reg, EVT VT) const;
37 
38   bool isHWTrueValue(SDValue Op) const;
39   bool isHWFalseValue(SDValue Op) const;
40 
41 public:
42   AMDGPUTargetLowering(TargetMachine &TM);
43 
44   virtual SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
45                              bool isVarArg,
46                              const SmallVectorImpl<ISD::InputArg> &Ins,
47                              DebugLoc DL, SelectionDAG &DAG,
48                              SmallVectorImpl<SDValue> &InVals) const;
49 
50   virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
51                               bool isVarArg,
52                               const SmallVectorImpl<ISD::OutputArg> &Outs,
53                               const SmallVectorImpl<SDValue> &OutVals,
54                               DebugLoc DL, SelectionDAG &DAG) const;
55 
56   virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
57   SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
58   SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
59   virtual const char* getTargetNodeName(unsigned Opcode) const;
60 
61 // Functions defined in AMDILISelLowering.cpp
62 public:
63 
64   /// computeMaskedBitsForTargetNode - Determine which of the bits specified
65   /// in Mask are known to be either zero or one and return them in the
66   /// KnownZero/KnownOne bitsets.
67   virtual void computeMaskedBitsForTargetNode(const SDValue Op,
68                                               APInt &KnownZero,
69                                               APInt &KnownOne,
70                                               const SelectionDAG &DAG,
71                                               unsigned Depth = 0) const;
72 
73   virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
74                                   const CallInst &I, unsigned Intrinsic) const;
75 
76   /// isFPImmLegal - We want to mark f32/f64 floating point values as legal.
77   bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
78 
79   /// ShouldShrinkFPConstant - We don't want to shrink f64/f32 constants.
80   bool ShouldShrinkFPConstant(EVT VT) const;
81 
82 private:
83   void InitAMDILLowering();
84   SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
85   SDValue LowerSREM8(SDValue Op, SelectionDAG &DAG) const;
86   SDValue LowerSREM16(SDValue Op, SelectionDAG &DAG) const;
87   SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
88   SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
89   SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
90   SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
91   SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
92   SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
93   SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
94   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
95   EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const;
96   SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
97   SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
98 };
99 
100 namespace AMDGPUISD
101 {
102 
103 enum
104 {
105   // AMDIL ISD Opcodes
106   FIRST_NUMBER = ISD::BUILTIN_OP_END,
107   MAD,         // 32bit Fused Multiply Add instruction
108   VBUILD,      // scalar to vector mov instruction
109   CALL,        // Function call based on a single integer
110   UMUL,        // 32bit unsigned multiplication
111   DIV_INF,      // Divide with infinity returned on zero divisor
112   RET_FLAG,
113   BRANCH_COND,
114   // End AMDIL ISD Opcodes
115   BITALIGN,
116   FRACT,
117   FMAX,
118   SMAX,
119   UMAX,
120   FMIN,
121   SMIN,
122   UMIN,
123   URECIP,
124   LAST_AMDGPU_ISD_NUMBER
125 };
126 
127 
128 } // End namespace AMDGPUISD
129 
130 namespace SIISD {
131 
132 enum {
133   SI_FIRST = AMDGPUISD::LAST_AMDGPU_ISD_NUMBER,
134   VCC_AND,
135   VCC_BITCAST
136 };
137 
138 } // End namespace SIISD
139 
140 } // End namespace llvm
141 
142 #endif // AMDGPUISELLOWERING_H
143