Searched refs:PredR (Results 1 – 5 of 5) sorted by relevance
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonEarlyIfConv.cpp | 108 FlowPattern() : SplitB(0), TrueB(0), FalseB(0), JoinB(0), PredR(0) {} in FlowPattern()
111 : SplitB(B), TrueB(TB), FalseB(FB), JoinB(JB), PredR(PR) {} in FlowPattern()
115 unsigned PredR; member
128 << ", PredR:" << PrintReg(P.FP.PredR, &P.TRI) in operator <<()
176 MachineInstr *MI, unsigned PredR, bool IfTrue);
179 unsigned PredR, bool IfTrue);
229 unsigned PredR = T1I->getOperand(0).getReg(); in matchFlowPattern() local
308 FP = FlowPattern(B, PredR, TB, FB, JB); in matchFlowPattern()
710 unsigned PredR, bool IfTrue) { in predicateInstr() argument
723 .addReg(PredR); in predicateInstr()
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| D | HexagonGenMux.cpp | 58 unsigned PredR; member
60 CondsetInfo() : PredR(0), TrueX(UINT_MAX), FalseX(UINT_MAX) {} in CondsetInfo()
69 unsigned DefR, PredR; member
75 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(D1), in MuxInfo()
216 if (F != CM.end() && F->second.PredR != PR) { in genMuxInBlock()
223 F->second.PredR = PR; in genMuxInBlock()
296 .addReg(MX.PredR) in genMuxInBlock()
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| D | HexagonExpandCondsets.cpp | 165 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond);
169 MachineBasicBlock::iterator Where, unsigned PredR, bool Cond);
170 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
775 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) { in getReachingDefForPred() argument
788 if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(MI))) in getReachingDefForPred()
798 if (RR.Reg == PredR) { in getReachingDefForPred()
887 MachineBasicBlock::iterator Where, unsigned PredR, bool Cond) { in predicateAt() argument
915 MB.addReg(PredR); in predicateAt()
941 unsigned PredR, bool Cond, MachineBasicBlock::iterator First, in renameInRange() argument
950 if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(MI))) in renameInRange()
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| D | HexagonHardwareLoops.cpp | 441 unsigned PredR, PredPos, PredRegFlags; in findInductionRegister() local
442 if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags)) in findInductionRegister()
445 MachineInstr *PredI = MRI->getVRegDef(PredR); in findInductionRegister()
1296 unsigned PredR = CmpI->getOperand(0).getReg(); in orderBumpCompare() local
1304 if (MO.getReg() == PredR) // Found an intervening use of PredR. in orderBumpCompare()
1875 unsigned PredR = PN->getOperand(i).getReg(); in createPreheaderForLoop() local
1881 MachineOperand MO = MachineOperand::CreateReg(PredR, false); in createPreheaderForLoop()
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| D | HexagonBitSimplify.cpp | 2687 unsigned PredR = 0; in processLoop() local
2688 if (!isSameShuffle(G.Out.Reg, G.Inp.Reg, F->PR.Reg, PredR)) { in processLoop()
2699 PredR = MRI->createVirtualRegister(RC); in processLoop()
2704 BuildMI(*C.PB, T, DL, HII->get(TfrI), PredR) in processLoop()
2707 PredR = F->PR.Reg; in processLoop()
2710 assert(MRI->getRegClass(PredR) == MRI->getRegClass(G.Inp.Reg)); in processLoop()
2711 moveGroup(G, *F->LB, *F->PB, F->LB->getFirstNonPHI(), F->DefR, PredR); in processLoop()
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