| /external/llvm/test/CodeGen/SystemZ/ |
| D | selectcc-03.ll | 8 ; CHECK: ipm [[REG:%r[0-5]]]
9 ; CHECK-NEXT: afi [[REG]], -268435456
10 ; CHECK-NEXT: sllg [[REG]], [[REG]], 32
11 ; CHECK-NEXT: srag %r2, [[REG]], 63
21 ; CHECK: ipm [[REG:%r[0-5]]]
22 ; CHECK-NEXT: xilf [[REG]], 268435456
23 ; CHECK-NEXT: afi [[REG]], -268435456
24 ; CHECK-NEXT: sllg [[REG]], [[REG]], 32
25 ; CHECK-NEXT: srag %r2, [[REG]], 63
35 ; CHECK: ipm [[REG:%r[0-5]]]
[all …]
|
| D | vec-div-01.ll | 9 ; CHECK: vlvgp [[REG:%v[0-9]+]],
10 ; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 0
11 ; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 1
12 ; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 2
13 ; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 3
14 ; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 4
15 ; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 5
16 ; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 6
17 ; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 8
18 ; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 9
[all …]
|
| D | vec-and-03.ll | 8 ; CHECK: vrepib [[REG:%v[0-9]+]], 1
9 ; CHECK: vn %v24, %v24, [[REG]]
19 ; CHECK: vrepih [[REG:%v[0-9]+]], 1
20 ; CHECK: vn %v24, %v24, [[REG]]
30 ; CHECK: vgbm [[REG:%v[0-9]+]], 21845
31 ; CHECK: vn %v24, %v24, [[REG]]
41 ; CHECK: vrepif [[REG:%v[0-9]+]], 1
42 ; CHECK: vn %v24, %v24, [[REG]]
52 ; CHECK: vgbm [[REG:%v[0-9]+]], 4369
53 ; CHECK: vn %v24, %v24, [[REG]]
[all …]
|
| D | vec-cmp-03.ll | 18 ; CHECK: vceqf [[REG:%v[0-9]+]], %v26, %v28
19 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
39 ; CHECK: vchf [[REG:%v[0-9]+]], %v28, %v26
40 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
50 ; CHECK: vchf [[REG:%v[0-9]+]], %v26, %v28
51 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
81 ; CHECK: vchlf [[REG:%v[0-9]+]], %v28, %v26
82 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
92 ; CHECK: vchlf [[REG:%v[0-9]+]], %v26, %v28
93 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
[all …]
|
| D | vec-cmp-02.ll | 18 ; CHECK: vceqh [[REG:%v[0-9]+]], %v26, %v28
19 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
39 ; CHECK: vchh [[REG:%v[0-9]+]], %v28, %v26
40 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
50 ; CHECK: vchh [[REG:%v[0-9]+]], %v26, %v28
51 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
81 ; CHECK: vchlh [[REG:%v[0-9]+]], %v28, %v26
82 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
92 ; CHECK: vchlh [[REG:%v[0-9]+]], %v26, %v28
93 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
[all …]
|
| D | vec-cmp-01.ll | 18 ; CHECK: vceqb [[REG:%v[0-9]+]], %v26, %v28
19 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
39 ; CHECK: vchb [[REG:%v[0-9]+]], %v28, %v26
40 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
50 ; CHECK: vchb [[REG:%v[0-9]+]], %v26, %v28
51 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
81 ; CHECK: vchlb [[REG:%v[0-9]+]], %v28, %v26
82 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
92 ; CHECK: vchlb [[REG:%v[0-9]+]], %v26, %v28
93 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
[all …]
|
| D | vec-cmp-04.ll | 18 ; CHECK: vceqg [[REG:%v[0-9]+]], %v26, %v28
19 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
39 ; CHECK: vchg [[REG:%v[0-9]+]], %v28, %v26
40 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
50 ; CHECK: vchg [[REG:%v[0-9]+]], %v26, %v28
51 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
81 ; CHECK: vchlg [[REG:%v[0-9]+]], %v28, %v26
82 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
92 ; CHECK: vchlg [[REG:%v[0-9]+]], %v26, %v28
93 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
[all …]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | big-endian-neon-extend.ll | 5 ; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16]
6 ; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
7 ; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
8 ; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
9 ; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]
10 ; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
20 ; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
21 ; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
22 ; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]]
23 ; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]
[all …]
|
| D | big-endian-vector-callee.ll | 6 ; SOFT: vmov [[REG:d[0-9]+]], r1, r0
7 ; SOFT: vadd.f64 [[REG]]
19 ; SOFT: vmov [[REG:d[0-9]+]], r1, r0
20 ; SOFT: vadd.i64 [[REG]]
32 ; SOFT: vmov [[REG:d[0-9]+]], r1, r0
33 ; SOFT: vrev64.32 [[REG]]
45 ; SOFT: vmov [[REG:d[0-9]+]], r1, r0
46 ; SOFT: vrev64.32 [[REG]]
58 ; SOFT: vmov [[REG:d[0-9]+]], r1, r0
59 ; SOFT: vrev64.16 [[REG]]
[all …]
|
| D | big-endian-vector-caller.ll | 7 ; SOFT: vadd.f64 [[REG:d[0-9]+]]
8 ; SOFT: vmov r1, r0, [[REG]]
23 ; SOFT: vadd.i64 [[REG:d[0-9]+]]
24 ; SOFT: vmov r1, r0, [[REG]]
39 ; SOFT: vrev64.32 [[REG:d[0-9]+]]
40 ; SOFT: vmov r1, r0, [[REG]]
55 ; SOFT: vrev64.32 [[REG:d[0-9]+]]
56 ; SOFT: vmov r1, r0, [[REG]]
71 ; SOFT: vrev64.16 [[REG:d[0-9]+]]
72 ; SOFT: vmov r1, r0, [[REG]]
[all …]
|
| D | big-endian-neon-trunc-store.ll | 5 ; CHECK: vmovn.i64 [[REG:d[0-9]+]]
6 ; CHECK: vrev32.16 [[REG]], [[REG]]
7 ; CHECK: vuzp.16 [[REG]], [[REG2:d[0-9]+]]
8 ; CHECK: vrev32.16 [[REG]], [[REG2]]
17 ; CHECK: vmovn.i32 [[REG:d[0-9]+]]
18 ; CHECK: vrev16.8 [[REG]], [[REG]]
19 ; CHECK: vuzp.8 [[REG]], [[REG2:d[0-9]+]]
20 ; CHECK: vrev32.8 [[REG]], [[REG2]]
|
| /external/llvm/test/CodeGen/X86/ |
| D | asm-mismatched-types.ll | 9 ; __asm__ __volatile__("# REG: %0" : : "r" (reg)); }
12 ; CHECK: # REG: %r8d
14 call void asm sideeffect "# REG: $0", "{r8}"(i32 %p)
19 ; CHECK: # REG: %r8d
21 call void asm sideeffect "# REG: $0", "{r8}"(float %p)
26 ; CHECK: # REG: %r9w
28 call void asm sideeffect "# REG: $0", "{r9}"(i16 %p)
33 ; CHECK: # REG: %bpl
35 call void asm sideeffect "# REG: $0", "{rbp}"(i8 %p)
40 ; CHECK: # REG: %r15w
[all …]
|
| D | xor.ll | 61 ; X64: notl [[REG:%[a-z]+]]
62 ; X64: andl {{.*}}[[REG]]
64 ; X32: notl [[REG:%[a-z]+]]
65 ; X32: andl {{.*}}[[REG]]
83 ; X64: notl [[REG:%[a-z]+]]
84 ; X64: andl {{.*}}[[REG]]
86 ; X32: notl [[REG:%[a-z]+]]
87 ; X32: andl {{.*}}[[REG]]
105 ; X64: notb [[REG:%[a-z]+]]
106 ; X64: andb {{.*}}[[REG]]
[all …]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | fast-isel-runtime-libcall.ll | 8 ; LARGE: adrp [[REG:x[0-9]+]], _fmodf@GOTPAGE
9 ; LARGE: ldr [[REG]], {{\[}}[[REG]], _fmodf@GOTPAGEOFF{{\]}}
10 ; LARGE-NEXT: blr [[REG]]
19 ; LARGE: adrp [[REG:x[0-9]+]], _fmod@GOTPAGE
20 ; LARGE: ldr [[REG]], {{\[}}[[REG]], _fmod@GOTPAGEOFF{{\]}}
21 ; LARGE-NEXT: blr [[REG]]
30 ; LARGE: adrp [[REG:x[0-9]+]], _sinf@GOTPAGE
31 ; LARGE: ldr [[REG]], {{\[}}[[REG]], _sinf@GOTPAGEOFF{{\]}}
32 ; LARGE-NEXT: blr [[REG]]
41 ; LARGE: adrp [[REG:x[0-9]+]], _sin@GOTPAGE
[all …]
|
| D | arm64-shifted-sext.ll | 8 ; CHECK: add [[REG:w[0-9]+]], w0, #1
9 ; CHECK: sbfiz w0, [[REG]], #4, #8
20 ; CHECK: add [[REG:w[0-9]+]], w0, #1
21 ; CHECK: sbfx w0, [[REG]], #4, #4
32 ; CHECK: add [[REG:w[0-9]+]], w0, #1
33 ; CHECK: sbfiz w0, [[REG]], #8, #8
44 ; CHECK: add [[REG:w[0-9]+]], w0, #1
45 ; CHECK: sxtb [[REG]], [[REG]]
46 ; CHECK: asr w0, [[REG]], #8
57 ; CHECK: add [[REG:w[0-9]+]], w0, #1
[all …]
|
| D | arm64-scvt.ll | 49 ; CHECK: ldr [[REG:w[0-9]+]], [x0]
50 ; CHECK: scvtf d0, [[REG]]
75 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
76 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
88 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
89 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
101 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
102 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
115 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], x[[REGNUM]]
116 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
[all …]
|
| D | fast-isel-int-ext3.ll | 10 ; CHECK: ldurb [[REG:w[0-9]+]], [x0, #-8]
11 ; CHECK: uxtb w0, [[REG]]
21 ; CHECK: ldurh [[REG:w[0-9]+]], [x0, #-8]
22 ; CHECK: uxth w0, [[REG]]
32 ; CHECK: ldurb w[[REG:[0-9]+]], [x0, #-8]
33 ; CHECK: ubfx x0, x[[REG]], #0, #8
43 ; CHECK: ldurh w[[REG:[0-9]+]], [x0, #-8]
44 ; CHECK: ubfx x0, x[[REG]], #0, #16
54 ; CHECK: ldur w[[REG:[0-9]+]], [x0, #-8]
55 ; CHECK: ubfx x0, x[[REG]], #0, #32
[all …]
|
| D | fast-isel-logic-op.ll | 7 ; CHECK: and [[REG:w[0-9]+]], w0, w1
14 ; CHECK: and [[REG:w[0-9]+]], w0, w1
15 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff
22 ; CHECK: and [[REG:w[0-9]+]], w0, w1
23 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff
79 ; CHECK: and [[REG:w[0-9]+]], w0, w1, lsl #4
80 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xff|#0xf0}}
88 ; CHECK: and [[REG:w[0-9]+]], w0, w1, lsl #8
89 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xffff|#0xff00}}
130 ; CHECK: orr [[REG:w[0-9]+]], w0, w1
[all …]
|
| D | fp16-vector-nvcast.ll | 6 ; CHECK-NEXT: movi v[[REG:[0-9]+]].2s, #0xab, lsl #16
7 ; CHECK-NEXT: str d[[REG]], [x0]
17 ; CHECK-NEXT: movi v[[REG:[0-9]+]].4h, #0xab
18 ; CHECK-NEXT: str d[[REG]], [x0]
28 ; CHECK-NEXT: movi v[[REG:[0-9]+]].8b, #0xab
29 ; CHECK-NEXT: str d[[REG]], [x0]
39 ; CHECK-NEXT: movi d[[REG:[0-9]+]], #0000000000000000
40 ; CHECK-NEXT: str d[[REG]], [x0]
49 ; CHECK-NEXT: movi v[[REG:[0-9]+]].4s, #0xab, lsl #16
50 ; CHECK-NEXT: str q[[REG]], [x0]
[all …]
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | float-to-int.ll | 12 ; CHECK: fctidz [[REG:[0-9]+]], 1
13 ; CHECK: stfd [[REG]],
18 ; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1
19 ; CHECK-VSX: stxsdx [[REG]],
29 ; CHECK: fctidz [[REG:[0-9]+]], 1
30 ; CHECK: stfd [[REG]],
35 ; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1
36 ; CHECK-VSX: stxsdx [[REG]],
46 ; CHECK: fctiduz [[REG:[0-9]+]], 1
47 ; CHECK: stfd [[REG]],
[all …]
|
| D | i32-to-float.ll | 14 ; CHECK: extsw [[REG:[0-9]+]], 3
15 ; CHECK: std [[REG]],
23 ; CHECK-PWR6: lfiwax [[REG:[0-9]+]],
24 ; CHECK-PWR6: fcfid [[REG2:[0-9]+]], [[REG]]
30 ; CHECK-A2: lfiwax [[REG:[0-9]+]],
31 ; CHECK-A2: fcfids 1, [[REG]]
36 ; CHECK-VSX: lfiwax [[REG:[0-9]+]],
37 ; CHECK-VSX: fcfids 1, [[REG]]
47 ; CHECK: extsw [[REG:[0-9]+]], 3
48 ; CHECK: std [[REG]],
[all …]
|
| D | fsel.ll | 37 ; CHECK-FM: fneg [[REG:[0-9]+]], 1
38 ; CHECK-FM: fsel 1, [[REG]], 3, 2
42 ; CHECK-FM-VSX: xsnegdp [[REG:[0-9]+]], 1
43 ; CHECK-FM-VSX: fsel 1, [[REG]], 3, 2
58 ; CHECK-FM: fsel [[REG:[0-9]+]], 1, 2, 3
60 ; CHECK-FM: fsel 1, [[REG2]], [[REG]], 3
65 ; CHECK-FM-VSX: fsel [[REG:[0-9]+]], 1, 2, 3
66 ; CHECK-FM-VSX: fsel 1, [[REG2]], [[REG]], 3
81 ; CHECK-FM: fsub [[REG:[0-9]+]], 2, 1
82 ; CHECK-FM: fsel 1, [[REG]], 1, 2
[all …]
|
| D | i64-to-float.ll | 13 ; CHECK: lfd [[REG:[0-9]+]],
14 ; CHECK: fcfids 1, [[REG]]
19 ; CHECK-VSX: lxsdx [[REG:[0-9]+]],
20 ; CHECK-VSX: fcfids 1, [[REG]]
31 ; CHECK: lfd [[REG:[0-9]+]],
32 ; CHECK: fcfid 1, [[REG]]
37 ; CHECK-VSX: lxsdx [[REG:[0-9]+]],
38 ; CHECK-VSX: xscvsxddp 1, [[REG]]
49 ; CHECK: lfd [[REG:[0-9]+]],
50 ; CHECK: fcfidus 1, [[REG]]
[all …]
|
| D | vsx.ll | 2 …u=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s
68 ; CHECK-REG-LABEL: @test5
69 ; CHECK-REG: xxlxor 34, 34, 35
70 ; CHECK-REG: blr
89 ; CHECK-REG-LABEL: @test6
90 ; CHECK-REG: xxlxor 34, 34, 35
91 ; CHECK-REG: blr
110 ; CHECK-REG-LABEL: @test7
111 ; CHECK-REG: xxlxor 34, 34, 35
112 ; CHECK-REG: blr
[all …]
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | imm.ll | 34 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
35 ; CHECK: buffer_store_dword [[REG]]
42 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
43 ; CHECK: buffer_store_dword [[REG]]
50 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
51 ; CHECK: buffer_store_dword [[REG]]
58 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0.5{{$}}
59 ; CHECK: buffer_store_dword [[REG]]
66 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -0.5{{$}}
67 ; CHECK: buffer_store_dword [[REG]]
[all …]
|