| /external/llvm/utils/crosstool/ |
| D | create-snapshots.sh | 20 readonly REV="${1:-$(getLatestRevisionFromSVN)}"
25 echo "Running: svn export -r ${REV} ${module}; log in ${log}"
26 svn -q export -r ${REV} ${LLVM_PROJECT_SVN}/${module}/trunk \
30 local tarball="${module}-${REV}.tar.bz2"
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| /external/llvm/docs/ |
| D | BigEndianNEON.rst | 78 …DR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can simulate either typ…
97 1. Insert a ``REV`` instruction to reverse the lane order after every ``LDR``.
133 … to avoid alignment faults (the result of the ``LD1`` would then need to be reversed with ``REV``).
145 | Lane ordering | ``LDR + REV`` | ``LD1`` |
147 | AAPCS | ``LDR`` | ``LD1 + REV`` |
149 | Alignment for strict mode | ``LDR`` / ``LD1 + REV`` | ``LD1`` |
161 2. Create code generation patterns for bitconverts that create ``REV`` instructions.
188 …REV`` undoing the ``LD1`` of type ``X`` (converting the in-register representation to the same as …
202 It turns out that these ``REV`` pairs can, in almost all cases, be squashed together into a single …
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| /external/libavc/encoder/ |
| D | ih264e_cabac.h | 55 #define REV(u4_input, u4_output) \ macro
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 919 REV = DataProcessing1SourceFixed | 0x00000800, enumerator
920 REV_w = REV,
921 REV32_x = REV | SixtyFourBits,
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| D | disasm-arm64.cc | 580 FORMAT(REV, "rev"); in VisitDataProcessing1Source()
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| D | assembler-arm64.cc | 1553 DataProcessing1Source(rd, rn, REV); in rev32()
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| /external/mdnsresponder/mDNSShared/ |
| D | CommonServices.h | 1182 #define NumVersionBuild( MAJOR, MINOR, BUGFIX, STAGE, REV ) \ argument
1187 ( ( ( REV ) & 0xFF ) ) )
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 342 # REV/REV16/REVSH
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| D | thumb2.txt | 1444 # REV
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| D | basic-arm-instructions.txt | 1201 # REV/REV16/REVSH
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| /external/vixl/src/vixl/a64/ |
| D | constants-a64.h | 1023 REV = DataProcessing1SourceFixed | 0x00000800, enumerator
1024 REV_w = REV,
1025 REV32_x = REV | SixtyFourBits,
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| D | disasm-a64.cc | 593 FORMAT(REV, "rev"); in VisitDataProcessing1Source()
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| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 472 @ REV/REV16/REVSH
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| D | basic-arm-instructions.s | 1855 @ REV/REV16/REVSH
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| D | basic-thumb2-instructions.s | 1932 @ REV
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| /external/jemalloc/ |
| D | Makefile.in | 39 REV := @rev@
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 5284 // conversions require one or more REV instructions.
5297 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
5300 // v1 = REV v2i32 (implicit)
5302 // v3 = REV v4i16 v2 (implicit)
5309 // v1 = REV v2i32 (implicit)
5310 // v2 = REV v2i32
5312 // v4 = REV v4i16
5313 // v5 = REV v4i16 v4 (implicit)
5316 // This means an extra two instructions, but actually in most cases the two REV
5320 // There is also no 128-bit REV instruction. This must be synthesized with an
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| D | AArch64SchedCyclone.td | 147 // CLS,CLZ,RBIT,REV,REV16,REV32
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| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 129 // CLZ,RBIT,REV,REV16,REVSH,PKH
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrArithmetic.td | 1218 // they don't have all the usual imm8 and REV forms, and are encoded into a
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| /external/wpa_supplicant_8/hostapd/ |
| D | ChangeLog | 978 * finished update from IEEE 802.1X-2001 to IEEE 802.1X-REV (now d11)
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| /external/owasp/sanitizer/lib/htmlparser-1.3/ |
| D | htmlparser-1.3-with-transitions.jar | META-INF/MANIFEST.MF
nu/validator/htmlparser/tools/XSLT4HTML5XOM.class
XSLT4HTML5XOM ... |
| D | htmlparser-1.3.jar | META-INF/MANIFEST.MF
nu/validator/htmlparser/tools/XSLT4HTML5XOM.class
XSLT4HTML5XOM ... |
| /external/vixl/doc/ |
| D | supported-instructions.md | 954 ### REV ### subsection
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| /external/valgrind/none/tests/arm64/ |
| D | integer.stdout.exp | 1802 REV
|