| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 61 int MCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { in getDwarfRegNum() argument
65 DwarfLLVMRegPair Key = { RegNum, 0 }; in getDwarfRegNum()
67 if (I == M+Size || I->FromReg != RegNum) in getDwarfRegNum()
72 int MCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { in getLLVMRegNum() argument
76 DwarfLLVMRegPair Key = { RegNum, 0 }; in getLLVMRegNum()
78 assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum"); in getLLVMRegNum()
82 int MCRegisterInfo::getSEHRegNum(unsigned RegNum) const { in getSEHRegNum()
83 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum); in getSEHRegNum()
84 if (I == L2SEHRegs.end()) return (int)RegNum; in getSEHRegNum()
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| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 184 unsigned RegNum; member
230 return Reg.RegNum; in getReg()
582 static std::unique_ptr<HexagonOperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg()
585 Op->Reg.RegNum = RegNum; in CreateReg()
1989 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); in processInstruction() local
1990 if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2 in processInstruction()
1993 r + llvm::utostr_32(RegNum) + Colon + llvm::utostr_32(RegNum - 1); in processInstruction()
1999 r + llvm::utostr_32(RegNum + 1) + Colon + llvm::utostr_32(RegNum); in processInstruction()
2008 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); in processInstruction() local
2009 if (RegNum & 1) { // Odd mapped to raw:hi in processInstruction()
[all …]
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| /external/llvm/test/CodeGen/X86/ |
| D | stackmap-large-constants.ll | 40 ; Dwarf RegNum
70 ; Dwarf RegNum
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 176 unsigned RegNum; member
181 unsigned RegNum; member
374 return Reg.RegNum; in getReg()
379 return VectorList.RegNum; in getVectorListStart()
925 Reg.RegNum); in isVectorRegLo()
929 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum); in isGPR32as64()
934 Reg.RegNum); in isWSeqPair()
939 Reg.RegNum); in isXSeqPair()
944 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].contains(Reg.RegNum); in isGPR64sp0()
1640 CreateReg(unsigned RegNum, bool isVector, SMLoc S, SMLoc E, MCContext &Ctx) { in CreateReg() argument
[all …]
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| /external/llvm/lib/CodeGen/ |
| D | StackMaps.cpp | 79 int RegNum = TRI->getDwarfRegNum(Reg, false); in getDwarfRegNum() local
80 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNum < 0; ++SR) in getDwarfRegNum()
81 RegNum = TRI->getDwarfRegNum(*SR, false); in getDwarfRegNum()
83 assert(RegNum >= 0 && "Invalid Dwarf register number."); in getDwarfRegNum()
84 return (unsigned)RegNum; in getDwarfRegNum()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 390 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
393 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
397 int getSEHRegNum(unsigned RegNum) const;
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| /external/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 184 unsigned RegNum; member
235 return Reg.RegNum; in getReg()
329 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, in CreateReg() argument
332 Op->Reg.RegNum = RegNum; in CreateReg()
362 Op.Reg.RegNum = IntPairRegs[regIdx / 2]; in MorphToIntPairReg()
373 Op.Reg.RegNum = DoubleRegs[regIdx / 2]; in MorphToDoubleReg()
396 Op.Reg.RegNum = Reg; in MorphToQuadReg()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 469 unsigned RegNum; member
474 unsigned RegNum; member
503 unsigned RegNum; member
600 return Reg.RegNum; in getReg()
1367 .contains(VectorList.RegNum)); in isVecListDPair()
1384 .contains(VectorList.RegNum)); in isVecListDPairSpaced()
1411 .contains(VectorList.RegNum)); in isVecListDPairAllLanes()
1686 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands() local
1687 Inst.addOperand(MCOperand::createReg(RegNum)); in addCondCodeOperands()
2109 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); in addAM3OffsetOperands()
[all …]
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| /external/clang/lib/Basic/ |
| D | TargetInfo.cpp | 377 if (AN == Name && ARN.RegNum < Names.size()) in isValidGCCRegisterName()
418 if (AN == Name && ARN.RegNum < Names.size()) in getNormalizedGCCRegisterName()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 265 unsigned RegNum = TRI->getEncodingValue(Reg); in printSavedRegsBitmask() local
270 FPUBitmask |= (1 << RegNum); in printSavedRegsBitmask()
273 FPUBitmask |= (3 << RegNum); in printSavedRegsBitmask()
277 CPUBitmask |= (1 << RegNum); in printSavedRegsBitmask()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDILCFGStructurizer.cpp | 239 MachineBasicBlock::iterator I, int NewOpcode, int RegNum,
241 void insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum);
518 MachineBasicBlock::iterator I, int NewOpcode, int RegNum, in insertCondBranchBefore() argument
524 MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false); in insertCondBranchBefore()
529 int NewOpcode, int RegNum) { in insertCondBranchEnd() argument
534 MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false); in insertCondBranchEnd()
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| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 2011 unsigned RegNum; in DecodeRegListOperand() local
2019 RegNum = RegLst & 0xf; in DecodeRegListOperand()
2022 if (RegNum > 9) in DecodeRegListOperand()
2025 for (unsigned i = 0; i < RegNum; i++) in DecodeRegListOperand()
2048 unsigned RegNum = RegLst & 0x3; in DecodeRegListOperand16() local
2050 for (unsigned i = 0; i <= RegNum; i++) in DecodeRegListOperand16()
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 1472 unsigned RegNum = GetX86RegNum(MO) << 4; in encodeInstruction() local
1474 RegNum |= 1 << 7; in encodeInstruction()
1482 RegNum |= Val; in encodeInstruction()
1485 EmitImmediate(MCOperand::createImm(RegNum), MI.getLoc(), 1, FK_Data_1, in encodeInstruction()
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| /external/llvm/docs/ |
| D | StackMaps.rst | 344 uint16 : Dwarf RegNum
350 uint16 : Dwarf RegNum
358 interpret the ``RegNum`` and ``Offset`` fields as follows:
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| /external/clang/include/clang/Basic/ |
| D | TargetInfo.h | 727 const unsigned RegNum; member
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILCFGStructurizer.cpp | 382 void addLoopBreakOnReg(LoopT *LoopRep, RegiT RegNum);
383 void addLoopContOnReg(LoopT *LoopRep, RegiT RegNum);
384 void addLoopBreakInitReg(LoopT *LoopRep, RegiT RegNum);
385 void addLoopContInitReg(LoopT *LoopRep, RegiT RegNum);
386 void addLoopEndbranchInitReg(LoopT *LoopRep, RegiT RegNum);
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| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 968 unsigned RegNum = MO.isUndef() ? UINT_MAX : TRI->getEncodingValue(Reg); in FormCandidates() local
972 if (RegNum <= PRegNum) in FormCandidates()
977 else if (!isNotVFP && RegNum != PRegNum+1) in FormCandidates()
996 PRegNum = RegNum; in FormCandidates()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1342 unsigned RegNum = Reg.EnumValue; in computeUberSets() local
1343 if (AllocatableRegs.count(RegNum)) in computeUberSets()
1346 UberSetIDs.join(0, RegNum); in computeUberSets()
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| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1033 auto GetRegisterName = [](unsigned RegNum) -> StringRef { in getShuffleComment() argument
1034 return X86ATTInstPrinter::getRegisterName(RegNum); in getShuffleComment()
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| D | X86ISelLowering.cpp | 26576 auto RegNum = Regs.size(); in combineVectorTruncationWithPACKUS() local
26578 j < e; j *= 2, RegNum /= 2) { in combineVectorTruncationWithPACKUS()
26579 for (unsigned i = 0; i < RegNum; i++) in combineVectorTruncationWithPACKUS()
26581 for (unsigned i = 0; i < RegNum / 2; i++) in combineVectorTruncationWithPACKUS()
26593 } else if (RegNum > 1) { in combineVectorTruncationWithPACKUS()
26594 Regs.resize(RegNum); in combineVectorTruncationWithPACKUS()
26666 unsigned RegNum = InVT.getSizeInBits() / 128; in combineVectorTruncation() local
26667 SmallVector<SDValue, 8> SubVec(RegNum); in combineVectorTruncation()
26669 for (unsigned i = 0; i < RegNum; i++) in combineVectorTruncation()
26673 for (unsigned i = 0; i < RegNum; i++) in combineVectorTruncation()
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 1122 if (unsigned RegNum = MO2.getReg()) { in printThumbAddrModeRROperand() local
1124 printRegName(O, RegNum); in printThumbAddrModeRROperand()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXAsmPrinter.cpp | 304 unsigned RegNum = RegMap[Reg]; in encodeVirtualRegister() local
326 Ret |= (RegNum & 0x0FFFFFFF); in encodeVirtualRegister()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 306 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
3879 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) { in matchRegisterByNumber() argument
3880 if (RegNum > in matchRegisterByNumber()
3884 return getReg(RegClass, RegNum); in matchRegisterByNumber()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 2584 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs() local
2590 if (RegNum != NumArgRegs && RegNum % 2 == 1) { in CC_PPC32_SVR4_Custom_AlignArgRegs()
2591 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
2612 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
2616 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
2617 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
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