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Searched refs:SALU (Results 1 – 12 of 12) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td21 field bits<1> SALU = 0;
53 let TSFlags{3} = SALU;
252 let SALU = 1;
263 let SALU = 1;
275 let SALU = 1;
289 let SALU = 1;
301 let SALU = 1;
DSIDefines.h19 SALU = 1 << 3, enumerator
DSIInstrInfo.h155 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
159 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
DSISchedule.td39 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
DSIInstructions.td1865 let hasSideEffects = 1, SALU = 1 in {
2045 let SALU = 1;
/external/llvm/test/CodeGen/AMDGPU/
Dsgpr-control-flow.ll4 ; Most SALU instructions ignore control flow, so we need to make sure
Dsplit-scalar-i64-add.ll6 ; SALU, but the upper half does not. The addc expects the carry bit
Dctpop64.ll113 ; FIXME: We currently disallow SALU instructions in all branches,
Dxor.ll152 ; use an SALU instruction for this.
Dctpop.ll271 ; FIXME: We currently disallow SALU instructions in all branches,
Dand.ll59 ; FIXME: We should really duplicate the constant so that the SALU use
/external/mesa3d/src/gallium/drivers/radeon/
DSIInstrInfo.td26 // Special bitcast node for sharing VCC register between VALU and SALU