| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 846 SETOGE, // 0 0 1 1 True if ordered and greater than or equal enumerator
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 132 setOperationAction(ISD::SETOGE, VT, Expand); in InitAMDILLowering()
556 cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE); in LowerSDIV24()
558 cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE); in LowerSDIV24()
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| D | AMDGPUInstructions.td | 59 case ISD::SETOGE: case ISD::SETUGE:
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| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 168 case FCmpInst::FCMP_OGE: return ISD::SETOGE; in getFCmpCondCode()
192 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrFloat.td | 60 defm GE : ComparisonFP<SETOGE, "ge ">;
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 332 case ISD::SETOGE: return "setoge"; in getOperationName()
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| D | TargetLowering.cpp | 145 case ISD::SETOGE: in softenSetCCOperands()
1844 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) in SimplifySetCC()
1845 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); in SimplifySetCC()
1847 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) in SimplifySetCC()
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| D | SelectionDAG.cpp | 1935 case ISD::SETOGE: in FoldSetCC()
1997 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || in FoldSetCC()
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| D | LegalizeDAG.cpp | 1856 case ISD::SETOGE: in LegalizeSetCCCondCode()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 2097 case ISD::SETOGE: in getPredicateForSetCC()
2142 case ISD::SETOGE: in getCRIdxForSetCC()
2165 case ISD::SETOLE: CC = ISD::SETOGE; Swap = true; break; in getVCmpInst()
2176 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break; in getVCmpInst()
2196 case ISD::SETOGE: in getVCmpInst()
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| D | PPCInstrQPX.td | 992 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETOGE),
1039 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETOGE),
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| D | PPCISelLowering.cpp | 353 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); in PPCTargetLowering()
354 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); in PPCTargetLowering()
6056 case ISD::SETOGE: in LowerSELECT_CC()
6092 case ISD::SETOGE: in LowerSELECT_CC()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructions.td | 86 [{return N->get() == ISD::SETOGE || N->get() == ISD::SETGE;}]
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| D | AMDGPUISelLowering.cpp | 1147 case ISD::SETOGE: in CombineFMinMaxLegacy()
1623 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE); in LowerDIVREM24()
2061 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE); in LowerFROUND32()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 580 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
953 (setcc node:$lhs, node:$rhs, SETOGE)>;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 191 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); in MipsSETargetLowering()
196 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); in MipsSETargetLowering()
323 setCondCodeAction(ISD::SETOGE, Ty, Expand); in addMSAFloatType()
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| D | MipsMSAInstrInfo.td | 161 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
162 def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
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| D | MipsISelLowering.cpp | 520 case ISD::SETOGE: return Mips::FCOND_OGE; in condCodeToFCC()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 954 (setcc node:$lhs, node:$rhs, SETOGE)>;
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1870 {ISD::SETOEQ, ISD::SETOGT, ISD::SETOLT, ISD::SETOGE, ISD::SETOLE, in HexagonTargetLowering()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1412 case ISD::SETOGE: return SPCC::FCC_GE; in FPCondCCodeToFCC()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1339 case ISD::SETOGE: CondCode = ARMCC::GE; break; in FPCCToARMCC()
3523 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE || in checkVSELConstraints()
4640 case ISD::SETOGE: in LowerVSETCC()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1094 case ISD::SETOGE: in changeFPCCToAArch64CC()
8982 (Op == ISD::FMAXNUM && CC != ISD::SETOGT && CC != ISD::SETOGE && in performAcrossLaneMinMaxReductionCombine()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 2185 case ISD::SETOGE: in getVectorComparison()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 4119 case ISD::SETOGE: in TranslateX86CC()
14221 case ISD::SETOGE: in translateX86FSETCC()
24019 case ISD::SETOGE: in PerformSELECTCombine()
24054 case ISD::SETOGE: in PerformSELECTCombine()
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