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Searched refs:SITargetLowering (Results 1 – 8 of 8) sorted by relevance

/external/mesa3d/src/gallium/drivers/radeon/
DSIISelLowering.cpp26 SITargetLowering::SITargetLowering(TargetMachine &TM) : in SITargetLowering() function in SITargetLowering
65 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter( in EmitInstrWithCustomInserter()
142 void SITargetLowering::AppendS_WAITCNT(MachineInstr *MI, MachineBasicBlock &BB, in AppendS_WAITCNT()
149 void SITargetLowering::LowerSI_INTERP(MachineInstr *MI, MachineBasicBlock &BB, in LowerSI_INTERP()
181 void SITargetLowering::LowerSI_INTERP_CONST(MachineInstr *MI, in LowerSI_INTERP_CONST()
203 void SITargetLowering::LowerSI_KIL(MachineInstr *MI, MachineBasicBlock &BB, in LowerSI_KIL()
235 void SITargetLowering::LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB, in LowerSI_V_CNDLT()
252 EVT SITargetLowering::getSetCCResultType(EVT VT) const in getSetCCResultType()
261 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const in LowerOperation()
293 SDValue SITargetLowering::Loweri1ContextSwitch(SDValue Op, in Loweri1ContextSwitch()
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DSIISelLowering.h22 class SITargetLowering : public AMDGPUTargetLowering
48 SITargetLowering(TargetMachine &tm);
DAMDGPUTargetMachine.cpp64 TLInfo = new SITargetLowering(*this); in AMDGPUTargetMachine()
/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp39 SITargetLowering::SITargetLowering(TargetMachine &TM, in SITargetLowering() function in SITargetLowering
295 bool SITargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &, in isShuffleMaskLegal()
302 bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const { in isLegalFlatAddressingMode()
308 bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const { in isLegalMUBUFAddressingMode()
343 bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL, in isLegalAddressingMode()
434 bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT, in allowsMisalignedMemoryAccesses()
476 EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, in getOptimalMemOpType()
502 bool SITargetLowering::isNoopAddrSpaceCast(unsigned SrcAS, in isNoopAddrSpaceCast()
508 bool SITargetLowering::isMemOpUniform(const SDNode *N) const { in isMemOpUniform()
523 SITargetLowering::getPreferredVectorAction(EVT VT) const { in getPreferredVectorAction()
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DSIISelLowering.h23 class SITargetLowering : public AMDGPUTargetLowering {
65 SITargetLowering(TargetMachine &tm, const AMDGPUSubtarget &STI);
DAMDGPUISelDAGToDAG.cpp170 const SITargetLowering *TL in isInlineImmediate()
171 = static_cast<const SITargetLowering *>(getTargetLowering()); in isInlineImmediate()
270 const SITargetLowering& Lowering = in glueCopyToM0()
271 *static_cast<const SITargetLowering*>(getTargetLowering()); in glueCopyToM0()
497 const SITargetLowering& Lowering = in Select()
498 *static_cast<const SITargetLowering*>(getTargetLowering()); in Select()
1006 const SITargetLowering& Lowering = in SelectMUBUFAddr64()
1007 *static_cast<const SITargetLowering*>(getTargetLowering()); in SelectMUBUFAddr64()
1076 const SITargetLowering& Lowering = in SelectMUBUFOffset()
1077 *static_cast<const SITargetLowering*>(getTargetLowering()); in SelectMUBUFOffset()
DAMDGPUSubtarget.cpp96 TLInfo.reset(new SITargetLowering(TM, *this)); in AMDGPUSubtarget()
DSIInstrInfo.td147 static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpUniform(N);