Searched refs:SRI (Results 1 – 11 of 11) sorted by relevance
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.cpp | 79 for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid()); in init() local
80 SRI.isValid(); in init()
81 ++SRI) in init()
82 if (!MCSubRegIterator(*SRI, &RI).isValid()) in init()
84 Uses.insert(*SRI); in init()
123 for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid()); in init() local
124 SRI.isValid(); in init()
125 ++SRI) { in init()
126 if (MCSubRegIterator(*SRI, &RI).isValid()) in init()
130 if (R == *SRI) { in init()
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| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 31 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubReg() local
32 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubReg()
33 if (*SRI == Idx) in getSubReg()
42 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubRegIndex() local
43 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubRegIndex()
45 return *SRI; in getSubRegIndex()
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| /external/llvm/lib/CodeGen/ |
| D | VirtRegMap.cpp | 269 LiveInterval::const_iterator &SRI = RangeIterPair.second; in addLiveInsForSubRanges() local
270 while (SRI != SR->end() && SRI->end <= MBBBegin) in addLiveInsForSubRanges()
271 ++SRI; in addLiveInsForSubRanges()
272 if (SRI == SR->end()) in addLiveInsForSubRanges()
274 if (SRI->start <= MBBBegin) in addLiveInsForSubRanges()
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| D | CriticalAntiDepBreaker.cpp | 273 for (MCSubRegIterator SRI(Reg, TRI, true); SRI.isValid(); ++SRI) { in ScanInstruction() local
274 unsigned SubregReg = *SRI; in ScanInstruction()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 267 SubRegMap::const_iterator SRI = Map.find(I->first); in computeSubRegs() local
268 if (SRI == Map.end()) in computeSubRegs()
272 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second)) in computeSubRegs()
275 SubRegs.insert(std::make_pair(I->second, SRI->second)); in computeSubRegs()
1438 for (CodeGenRegister::SubRegMap::const_iterator SRI = SRM.begin(), in normalizeWeight() local
1439 SRE = SRM.end(); SRI != SRE; ++SRI) { in normalizeWeight()
1440 if (SRI->second == Reg) in normalizeWeight()
1443 Changed |= normalizeWeight(SRI->second, UberSets, RegSets, in normalizeWeight()
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| D | CodeGenSchedule.cpp | 278 for (RecIter SRI = SRDefs.begin(), SRE = SRDefs.end(); SRI != SRE; ++SRI) { in collectSchedRW() local
279 assert(!getSchedRWIdx(*SRI, /*IsRead-*/true) && "duplicate SchedWrite"); in collectSchedRW()
280 SchedReads.emplace_back(SchedReads.size(), *SRI); in collectSchedRW()
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| /external/iputils/doc/ |
| D | rdisc.sgml | 189 RFC1256</ulink>, Network Information Center, SRI International,
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 2773 unsigned SRI; in Select() local
2776 case 0: SRI = PPC::sub_lt; break; in Select()
2777 case 1: SRI = PPC::sub_gt; break; in Select()
2778 case 2: SRI = PPC::sub_eq; break; in Select()
2779 case 3: SRI = PPC::sub_un; break; in Select()
2782 SDValue CCBit = CurDAG->getTargetExtractSubreg(SRI, dl, MVT::i1, CCReg); in Select()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 494 // SLI,SRI
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| D | AArch64InstrInfo.td | 4629 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
4678 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>;
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| /external/vixl/doc/ |
| D | supported-instructions.md | 3652 ### SRI ### subsection
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