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Searched refs:ShiftTy (Results 1 – 7 of 7) sorted by relevance

/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp505 ARM_AM::ShiftOpc ShiftTy; member
515 ARM_AM::ShiftOpc ShiftTy; member
522 ARM_AM::ShiftOpc ShiftTy; member
1042 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; in isPostIdxReg()
1163 return PostIdxReg.ShiftTy == ARM_AM::no_shift; in isAM3Offset()
1732 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); in addRegShiftedRegOperands()
1743 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); in addRegShiftedImmOperands()
2316 PostIdxReg.ShiftTy); in addPostIdxRegShiftedOperands()
2546 Op->RegShiftedReg.ShiftTy = ShTy; in CreateShiftedRegister()
2559 Op->RegShiftedImm.ShiftTy = ShTy; in CreateShiftedImmediate()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp1715 EVT ShiftTy = DCI.isBeforeLegalize() in SimplifySetCC() local
1724 ShiftTy))); in SimplifySetCC()
1733 ShiftTy))); in SimplifySetCC()
1750 EVT ShiftTy = DCI.isBeforeLegalize() in SimplifySetCC() local
1756 ShiftTy)); in SimplifySetCC()
1782 EVT ShiftTy = DCI.isBeforeLegalize() in SimplifySetCC() local
1787 DAG.getConstant(ShiftBits, dl, ShiftTy)); in SimplifySetCC()
DLegalizeIntegerTypes.cpp2272 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout()); in ExpandIntRes_Shift() local
2273 assert(ShiftTy.getScalarType().getSizeInBits() >= in ExpandIntRes_Shift()
2276 if (ShiftOp.getValueType() != ShiftTy) in ExpandIntRes_Shift()
2277 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); in ExpandIntRes_Shift()
DSelectionDAGBuilder.cpp2341 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy( in visitShift() local
2345 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { in visitShift()
2346 unsigned ShiftSize = ShiftTy.getSizeInBits(); in visitShift()
2352 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); in visitShift()
2359 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); in visitShift()
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp797 EVT ShiftTy, SelectionDAG &DAG) { in genConstMult() argument
812 DAG.getConstant(Log2_64(C), DL, ShiftTy)); in genConstMult()
822 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); in genConstMult()
823 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); in genConstMult()
829 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG); in genConstMult()
830 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG); in genConstMult()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp163 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
2753 ARM_AM::ShiftOpc ShiftTy) { in SelectShift() argument
2796 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); in SelectShift()
2799 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0)); in SelectShift()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp25741 EVT ShiftTy = Shift.getValueType(); in foldXorTruncShiftIntoCmp() local
25742 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64) in foldXorTruncShiftIntoCmp()
25747 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1) in foldXorTruncShiftIntoCmp()