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Searched refs:Src1Reg (Results 1 – 9 of 9) sorted by relevance

/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp181 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
320 Src1Reg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
322 if (HexagonMCInstrInfo::isIntReg(Src1Reg) && in getDuplexCandidateGroup()
324 Hexagon::R29 == Src1Reg && inRange<5, 2>(MCI, 1)) { in getDuplexCandidateGroup()
328 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getDuplexCandidateGroup()
336 Src1Reg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
338 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getDuplexCandidateGroup()
355 Src1Reg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
357 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getDuplexCandidateGroup()
365 Src1Reg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
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DHexagonMCCompound.cpp84 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
101 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
104 HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getCompoundCandidateGroup()
146 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
148 HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getCompoundCandidateGroup()
160 Src1Reg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
161 if (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg) in getCompoundCandidateGroup()
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.cpp909 unsigned Src1Reg = MI->getOperand(1).getReg(); in expandPostRAPseudo() local
911 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::subreg_hireg); in expandPostRAPseudo()
912 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::subreg_loreg); in expandPostRAPseudo()
931 unsigned Src1Reg = MI->getOperand(1).getReg(); in expandPostRAPseudo() local
934 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::subreg_hireg); in expandPostRAPseudo()
935 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::subreg_loreg); in expandPostRAPseudo()
2839 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
2854 Src1Reg = MI->getOperand(1).getReg(); in getCompoundCandidateGroup()
2858 isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg)) in getCompoundCandidateGroup()
2891 Src1Reg = MI->getOperand(1).getReg(); in getCompoundCandidateGroup()
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/external/llvm/lib/Target/ARM/
DMLxExpansionPass.cpp278 unsigned Src1Reg = MI->getOperand(2).getReg(); in ExpandFPMLxInstruction() local
294 .addReg(Src1Reg, getKillRegState(Src1Kill)) in ExpandFPMLxInstruction()
/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp981 unsigned Src1Reg = getRegForValue(SI->getTrueValue()); in selectSelect() local
985 if (!Src1Reg || !Src2Reg || !CondReg) in selectSelect()
1003 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg); in selectSelect()
1672 unsigned Src1Reg = getRegForValue(I->getOperand(1)); in selectDivRem() local
1673 if (!Src0Reg || !Src1Reg) in selectDivRem()
1676 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg); in selectDivRem()
1677 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7); in selectDivRem()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp2536 unsigned Src1Reg = getRegForValue(Src1Val); in optimizeSelect() local
2537 if (!Src1Reg) in optimizeSelect()
2547 Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, Src1IsKill, 1); in optimizeSelect()
2550 unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg, in optimizeSelect()
2666 unsigned Src1Reg = getRegForValue(SI->getTrueValue()); in selectSelect() local
2672 if (!Src1Reg || !Src2Reg) in selectSelect()
2676 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect()
2680 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect()
4454 unsigned Src1Reg = getRegForValue(I->getOperand(1)); in selectRem() local
4455 if (!Src1Reg) in selectRem()
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/external/llvm/lib/Target/AMDGPU/
DR600InstrInfo.h246 unsigned Src1Reg = 0) const;
DR600InstrInfo.cpp1180 unsigned Src1Reg) const { in buildDefaultInstruction()
1184 if (Src1Reg) { in buildDefaultInstruction()
1198 if (Src1Reg) { in buildDefaultInstruction()
1199 MIB.addReg(Src1Reg) // $src1 in buildDefaultInstruction()
DSIInstrInfo.cpp1097 unsigned Src1Reg = Src1->getReg(); in FoldImmediate() local
1101 Src0->setReg(Src1Reg); in FoldImmediate()