| /external/v8/src/mips/ |
| D | constants-mips.cc | 226 case TEQ: in IsTrap()
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| D | constants-mips.h | 439 TEQ = ((6U << 3) + 4), enumerator
927 FunctionFieldToBitNumber(TEQ) | FunctionFieldToBitNumber(TNE) |
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| D | disasm-mips.cc | 432 case TEQ: in PrintCode()
1188 case TEQ: in DecodeTypeRegisterSPECIAL()
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| D | assembler-mips.cc | 1951 SPECIAL | TEQ | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; in teq()
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| D | simulator-mips.cc | 3712 case TEQ: in DecodeTypeRegisterSPECIAL()
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| /external/v8/src/mips64/ |
| D | constants-mips64.cc | 226 case TEQ: in IsTrap()
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| D | constants-mips64.h | 449 TEQ = ((6U << 3) + 4), enumerator
984 FunctionFieldToBitNumber(TEQ) | FunctionFieldToBitNumber(TNE) |
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| D | disasm-mips64.cc | 447 case TEQ: in PrintCode()
1397 case TEQ: in DecodeTypeRegisterSPECIAL()
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| D | assembler-mips64.cc | 2236 SPECIAL | TEQ | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; in teq()
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| D | simulator-mips64.cc | 3783 case TEQ: in DecodeTypeRegisterSPECIAL()
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| /external/tremolo/Tremolo/ |
| D | mdctLARM.s | 69 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
74 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
79 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
84 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
100 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
137 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
142 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
147 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
152 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
169 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
[all …]
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| D | mdctARM.s | 71 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
76 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
81 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
86 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
102 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
139 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
144 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
149 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
154 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
171 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
[all …]
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| /external/v8/src/arm/ |
| D | constants-arm.h | 150 TEQ = 9 << 21, // Test Equivalence. enumerator
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| D | disasm-arm.cc | 896 case TEQ: { in DecodeType01()
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| D | simulator-arm.cc | 2448 case TEQ: { in DecodeType01()
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| D | assembler-arm.cc | 1473 addrmod1(cond | TEQ | S, src1, r0, src2); in teq()
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| /external/llvm/test/MC/ARM/ |
| D | diagnostics.s | 668 TEQ r7, #-2149, #0
669 TEQ r7, #100, #1
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| D | basic-arm-instructions.s | 3121 @ TEQ
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 2950 emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, Instructions); in expandDiv()
2967 emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, Instructions); in expandDiv()
2983 emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, Instructions); in expandDiv()
3019 emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, Instructions); in expandDiv()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1677 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7); in selectDivRem()
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| D | MipsInstrInfo.td | 1459 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
1893 (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
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| D | MipsISelLowering.cpp | 921 MIB = BuildMI(MBB, std::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ)) in insertDivByZeroTrap()
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 2283 # TEQ
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| D | basic-arm-instructions.txt | 2142 # TEQ
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 4435 // Note that TST/TEQ don't set all the same flags that CMP does!
4440 defm TEQ : AI1_cmp_irs<0b1001, "teq",
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