| /external/llvm/test/CodeGen/AMDGPU/ |
| D | llvm.AMDGPU.bfm.ll | 5 declare i32 @llvm.AMDGPU.bfm(i32, i32) nounwind readnone
11 %bfm = call i32 @llvm.AMDGPU.bfm(i32 %src0, i32 %src1) nounwind readnone
12 store i32 %bfm, i32 addrspace(1)* %out, align 4
20 %bfm = call i32 @llvm.AMDGPU.bfm(i32 %src0, i32 123) nounwind readnone
21 store i32 %bfm, i32 addrspace(1)* %out, align 4
29 %bfm = call i32 @llvm.AMDGPU.bfm(i32 123, i32 %src1) nounwind readnone
30 store i32 %bfm, i32 addrspace(1)* %out, align 4
38 %bfm = call i32 @llvm.AMDGPU.bfm(i32 123, i32 456) nounwind readnone
39 store i32 %bfm, i32 addrspace(1)* %out, align 4
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-bitfield-encoding.s | 8 bfm w1, w2, #1, #15
9 bfm x1, x2, #1, #15
|
| D | basic-a64-diagnostics.s | 815 bfm w3, w5, #32, #1
816 bfm w7, w11, #19, #32
817 bfm x29, x30, #64, #0
818 bfm x10, x20, #63, #64
|
| D | basic-a64-instructions.s | 975 bfm x4, x5, #12, #10
976 bfm xzr, x4, #0, #0
977 bfm x4, xzr, #63, #5
978 bfm x5, x6, #12, #63
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-bitfield-extract.ll | 105 ; Check if we can still catch bfm instruction when we drop some low bits
126 ; Check if we can still catch bfm instruction when we drop some high bits
147 ; Check if we can still catch bfm instruction when we drop some low bits
169 ; Check if we can still catch bfm instruction when we drop some high bits
190 ; Check if we can catch bfm instruction when lsb is 0 (i.e., no lshr)
210 ; Check if we can catch bfm instruction when lsb is 0 (i.e., no lshr)
239 ; Check if we can still catch bfm instruction when we drop some high bits
261 ; Check if we can still catch bfm instruction when we drop some high bits
285 ; Check if we can still catch bfm instruction when we drop some high bits
314 ; Check if we can still catch bfm instruction when we drop some high bits
[all …]
|
| D | bitfield-insert.ll | 144 ; CHECK-NOT: bfm
164 ; CHECK-NOT: bfm
|
| /external/vixl/doc/ |
| D | changelog.md | 33 + MacroAssembler support for `bfm`, `ubfm` and `sbfm`.
|
| D | supported-instructions.md | 150 void bfm(const Register& rd,
|
| /external/v8/src/arm64/ |
| D | assembler-arm64.h | 1122 void bfm(const Register& rd, const Register& rn, int immr, int imms);
1135 bfm(rd, rn, (rd.SizeInBits() - lsb) & (rd.SizeInBits() - 1), width - 1); in bfi()
1142 bfm(rd, rn, lsb, lsb + width - 1); in bfxil()
|
| D | assembler-arm64.cc | 1284 void Assembler::bfm(const Register& rd, const Register& rn, int immr, in bfm() function in v8::internal::Assembler
|
| /external/vixl/src/vixl/a64/ |
| D | assembler-a64.h | 1422 void bfm(const Register& rd,
1447 bfm(rd, rn, (rd.size() - lsb) & (rd.size() - 1), width - 1); in bfi()
1457 bfm(rd, rn, lsb, lsb + width - 1); in bfxil()
|
| D | macro-assembler-a64.h | 986 bfm(rd, rn, immr, imms); in Bfm()
|
| D | assembler-a64.cc | 1087 void Assembler::bfm(const Register& rd, in bfm() function in vixl::Assembler
|
| /external/v8/test/cctest/ |
| D | test-assembler-arm64.cc | 4871 TEST(bfm) { in TEST() argument
4885 __ bfm(x10, x1, 16, 31); in TEST() local
4886 __ bfm(x11, x1, 32, 15); in TEST() local
4888 __ bfm(w20, w1, 16, 23); in TEST() local
4889 __ bfm(w21, w1, 24, 15); in TEST() local
|
| /external/valgrind/none/tests/arm64/ |
| D | integer.stdout.exp | 148 bfm x2, x4, #0, #63 :: rd 5555555555555555 rn 5555555555555555, cin 0, nzcv 00000000
149 bfm x2, x4, #0, #63 :: rd aaaaaaaaaaaaaaaa rn aaaaaaaaaaaaaaaa, cin 0, nzcv 00000000
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 956 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
|
| /external/vixl/test/ |
| D | test-assembler-a64.cc | 8954 TEST(bfm) { in TEST() argument
|