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Searched refs:bpe (Results 1 – 6 of 6) sorted by relevance

/external/libdrm/radeon/
Dradeon_surface.c164 unsigned bpe, unsigned level, in surf_minify() argument
186 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; in surf_minify()
275 xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear()
279 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); in r6_surface_init_linear()
285 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); in r6_surface_init_linear()
306 xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear_aligned()
313 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); in r6_surface_init_linear_aligned()
332 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples); in r6_surface_init_1d()
337 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); in r6_surface_init_1d()
346 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); in r6_surface_init_1d()
[all …]
Dradeon_surface.h119 uint32_t bpe; member
/external/drm_gralloc/
Dgralloc_drm_radeon.c81 static int radeon_get_pitch_align(struct radeon_info *info, int bpe, uint32_t tiling) in radeon_get_pitch_align() argument
88 pitch_align = (((info->group_bytes / 8) / bpe) * in radeon_get_pitch_align()
94 pitch_align = MAX(8, (info->group_bytes / (8 * bpe))); in radeon_get_pitch_align()
96 pitch_align = MAX(info->group_bytes / bpe, pitch_align); in radeon_get_pitch_align()
100 pitch_align = MAX(64, info->group_bytes / bpe); in radeon_get_pitch_align()
113 pitch_align = 256 / bpe; in radeon_get_pitch_align()
146 int bpe, uint32_t tiling) in radeon_get_base_align() argument
148 int pixel_align = radeon_get_pitch_align(info, bpe, tiling); in radeon_get_base_align()
154 base_align = MAX(info->num_banks * info->num_channels * 8 * 8 * bpe, in radeon_get_base_align()
155 pixel_align * bpe * height_align); in radeon_get_base_align()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_texture.c93 surface->bpe = 4; /* stencil is allocated separately on evergreen */ in r600_init_surface()
95 surface->bpe = util_format_get_blocksize(ptex->format); in r600_init_surface()
97 if (surface->bpe == 3) { in r600_init_surface()
98 surface->bpe = 4; in r600_init_surface()
178 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe; in r600_setup_surface()
271 fmask.bpe = 4; in r600_texture_get_fmask_info()
275 fmask.bpe = 8; in r600_texture_get_fmask_info()
279 fmask.bpe = 16; in r600_texture_get_fmask_info()
289 fmask.bpe *= 2; in r600_texture_get_fmask_info()
322 fmask.npix_x, fmask.npix_y, fmask.bpe * fmask.nsamples, rtex->fmask_size); in r600_texture_allocate_fmask()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dr600_texture.c88 surface->bpe = util_format_get_blocksize(ptex->format); in r600_init_surface()
90 if (surface->bpe == 3) { in r600_init_surface()
91 surface->bpe = 4; in r600_init_surface()
168 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe; in r600_setup_surface()
/external/v8/src/runtime/
Druntime-simd.cc914 size_t bpe = tarray->element_size(); \
917 RUNTIME_ASSERT(index >= 0 && index * bpe + bytes <= byte_length); \
923 memcpy(lanes, tarray_base + index * bpe, bytes); \
933 size_t bpe = tarray->element_size(); \
936 RUNTIME_ASSERT(index >= 0 && index * bpe + bytes <= byte_length); \
945 memcpy(tarray_base + index * bpe, lanes, bytes);