Searched refs:constrainOperandRegClass (Results 1 – 6 of 6) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 292 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_r()
315 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rr()
316 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rr()
344 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rrr()
345 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rrr()
346 Op2 = constrainOperandRegClass(II, Op1, 3); in fastEmitInst_rrr()
375 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_ri()
402 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rri()
403 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rri()
570 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); in ARMMaterializeInt()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1766 unsigned FastISel::constrainOperandRegClass(const MCInstrDesc &II, unsigned Op, in constrainOperandRegClass() function in FastISel
1798 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
1820 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
1821 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
1845 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
1846 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrr()
1847 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrr()
1871 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_ri()
1894 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rii()
1938 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rri()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 1070 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx)); in addLoadStoreOperands()
1072 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1)); in addLoadStoreOperands()
1269 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1270 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rr()
1314 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1354 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1355 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rs()
1397 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
1398 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rx()
2053 SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs()); in emitStore()
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| /external/llvm/include/llvm/CodeGen/ |
| D | FastISel.h | 472 unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1866 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
1867 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 257 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
3590 unsigned IndexReg = constrainOperandRegClass(Result->getDesc(), in tryToFoldLoadIntoMI()
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