| /external/llvm/test/CodeGen/AArch64/ |
| D | cond-sel.ll | 107 ; CHECK: csinv {{w[0-9]+}}, [[LHS]], [[RHS]], ls
115 ; CHECK: csinv {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le
124 ; CHECK: csinv {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls
132 ; CHECK: csinv {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le
|
| D | arm64-early-ifcvt.ll | 114 ; CHECK-NEXT: csinv w0, w1, w0, eq
132 ; CHECK-NEXT: csinv x0, x1, x0, eq
150 ; CHECK-NEXT: csinv w0, w1, w0, ne
168 ; CHECK-NEXT: csinv x0, x1, x0, ne
|
| D | arm64-csel.ll | 104 ; CHECK: csinv w0, w1, w2, ne
|
| /external/valgrind/none/tests/arm64/ |
| D | integer.stdout.exp | 867 cmp x17,x18 ; csinv x16,x17,x18,eq :: rd 8593c2e5aedb9b6a rm afa6ef803bc9291c, rn 7a6c3d1a51246495,…
868 cmp x17,x18 ; csinv x16,x17,x18,ne :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495,…
869 cmp x17,x18 ; csinv x16,x17,x18,cc :: rd 8593c2e5aedb9b6a rm afa6ef803bc9291c, rn 7a6c3d1a51246495,…
870 cmp x17,x18 ; csinv x16,x17,x18,cs :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495,…
871 cmp x17,x18 ; csinv x16,x17,x18,mi :: rd 8593c2e5aedb9b6a rm afa6ef803bc9291c, rn 7a6c3d1a51246495,…
872 cmp x17,x18 ; csinv x16,x17,x18,pl :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495,…
873 cmp x17,x18 ; csinv x16,x17,x18,vc :: rd 8593c2e5aedb9b6a rm afa6ef803bc9291c, rn 7a6c3d1a51246495,…
874 cmp x17,x18 ; csinv x16,x17,x18,vs :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495,…
900 cmp w17,w18 ; csinv w16,w17,w18,eq :: rd 00000000aedb9b6a rm afa6ef803bc9291c, rn 7a6c3d1a51246495,…
901 cmp w17,w18 ; csinv w16,w17,w18,ne :: rd 000000003bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495,…
[all …]
|
| /external/llvm/test/MC/AArch64/ |
| D | basic-a64-instructions.s | 1365 csinv w1, w0, w19, ne
1366 csinv wzr, w5, w9, eq
1367 csinv w9, wzr, w30, gt
1368 csinv w1, w28, wzr, mi
1374 csinv x19, x23, x29, lt
1375 csinv xzr, x3, x4, ge
1376 csinv x5, xzr, x6, cs
1377 csinv x7, x8, xzr, cc
|
| D | arm64-arithmetic-encoding.s | 554 csinv w1, w2, w3, eq
555 csinv x1, x2, x3, eq
|
| D | basic-a64-diagnostics.s | 1366 csinv w20, wsp, wsp, mi
1367 csinv sp, x30, x29, le
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-arithmetic.txt | 520 # CHECK: csinv w1, w2, w3, eq
522 # CHECK: csinv x1, x2, x3, eq
|
| D | basic-a64-instructions.txt | 911 # CHECK: csinv w1, w0, w19, ne
912 # CHECK: csinv wzr, w5, w9, eq
913 # CHECK: csinv w9, wzr, w30, gt
914 # CHECK: csinv w1, w28, wzr, mi
915 # CHECK: csinv x19, x23, x29, lt
916 # CHECK: csinv xzr, x3, x4, ge
917 # CHECK: csinv x5, xzr, x6, hs
918 # CHECK: csinv x7, x8, xzr, lo
951 # CHECK: csinv x3, xzr, xzr, nv
984 # CHECK: csinv x1, x0, x0, al
[all …]
|
| /external/v8/test/cctest/ |
| D | test-disasm-arm64.cc | 1283 COMPARE(csinv(w12, w13, w14, mi), "csinv w12, w13, w14, mi"); in TEST_()
1284 COMPARE(csinv(x15, x16, x17, pl), "csinv x15, x16, x17, pl"); in TEST_()
1302 COMPARE(csinv(x4, x5, x6, al), "csinv x4, x5, x6, al"); in TEST_()
1303 COMPARE(csinv(x5, x6, x7, nv), "csinv x5, x6, x7, nv"); in TEST_()
|
| /external/v8/src/arm64/ |
| D | assembler-arm64.cc | 1343 void Assembler::csinv(const Register& rd, in csinv() function in v8::internal::Assembler
1369 csinv(rd, zr, zr, NegateCondition(cond)); in csetm()
1381 csinv(rd, rn, rn, NegateCondition(cond)); in cinv()
|
| D | macro-assembler-arm64-inl.h | 499 csinv(rd, rn, rm, cond); in Csinv()
|
| D | assembler-arm64.h | 1241 void csinv(const Register& rd,
|
| D | macro-assembler-arm64.cc | 395 csinv(rd, rn, zr, cond); in Csel()
|
| /external/vixl/src/vixl/a64/ |
| D | assembler-a64.cc | 1147 void Assembler::csinv(const Register& rd, in csinv() function in vixl::Assembler
1173 csinv(rd, zr, zr, InvertCondition(cond)); in csetm()
1185 csinv(rd, rn, rn, InvertCondition(cond)); in cinv()
|
| D | macro-assembler-a64.cc | 1135 csinv(rd, rn, zr, cond); in Csel()
|
| D | macro-assembler-a64.h | 1109 csinv(rd, rn, rm, cond); in Csinv()
|
| D | assembler-a64.h | 1570 void csinv(const Register& rd,
|
| /external/vixl/test/ |
| D | test-disasm-a64.cc | 2172 COMPARE(csinv(w12, w13, w14, mi), "csinv w12, w13, w14, mi"); in TEST()
2173 COMPARE(csinv(x15, x16, x17, pl), "csinv x15, x16, x17, pl"); in TEST()
2191 COMPARE(csinv(x4, x5, x6, al), "csinv x4, x5, x6, al"); in TEST()
2192 COMPARE(csinv(x5, x6, x7, nv), "csinv x5, x6, x7, nv"); in TEST()
|
| /external/vixl/doc/ |
| D | supported-instructions.md | 433 void csinv(const Register& rd,
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 1068 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
|