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/external/llvm/lib/Target/X86/
DX86Schedule.td17 def ReadAfterLd : SchedRead;
21 def WriteRMW : SchedWrite;
35 def Ld : SchedWrite;
37 def NAME : X86FoldableSchedWrite {
45 def WriteIMulH : SchedWrite; // Integer multiplication, high part.
47 def WriteLEA : SchedWrite; // LEA instructions can't fold loads.
53 def WriteLoad : SchedWrite;
54 def WriteStore : SchedWrite;
55 def WriteMove : SchedWrite;
59 def WriteZero : SchedWrite;
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/external/llvm/lib/Target/ARM/
DARMSchedule.td32 // def WriteALUsr : SchedWrite;
33 // def ReadAdvanceALUsr : ScheRead;
36 // def ADDrs : I<>, Sched<[WriteALUsr, ReadAdvanceALUsr, ReadDefault,
45 // def P01 : ProcResource<3>; // ALU unit (3 of it).
48 // def : WriteRes<WriteALUsr, [P01, P01]> {
55 // def : ReadAdvance<ReadAdvanceALUsr, 3>;
58 def WriteALU : SchedWrite;
59 def ReadALU : SchedRead;
62 def WriteALUsi : SchedWrite; // Shift by immediate.
63 def WriteALUsr : SchedWrite; // Shift by register.
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/external/clang/include/clang/Basic/
DStmtNodes.td12 def NullStmt : Stmt;
13 def CompoundStmt : Stmt;
14 def LabelStmt : Stmt;
15 def AttributedStmt : Stmt;
16 def IfStmt : Stmt;
17 def SwitchStmt : Stmt;
18 def WhileStmt : Stmt;
19 def DoStmt : Stmt;
20 def ForStmt : Stmt;
21 def GotoStmt : Stmt;
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DDeclNodes.td13 def TranslationUnit : Decl, DeclContext;
14 def ExternCContext : Decl, DeclContext;
15 def Named : Decl<1>;
16 def Namespace : DDecl<Named>, DeclContext;
17 def UsingDirective : DDecl<Named>;
18 def NamespaceAlias : DDecl<Named>;
19 def Label : DDecl<Named>;
20 def Type : DDecl<Named, 1>;
21 def TypedefName : DDecl<Type, 1>;
22 def Typedef : DDecl<TypedefName>;
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DDiagnosticGroups.td10 def ImplicitFunctionDeclare : DiagGroup<"implicit-function-declaration">;
11 def ImplicitInt : DiagGroup<"implicit-int">;
14 def Implicit : DiagGroup<"implicit", [
20 def : DiagGroup<"abi">;
21 def AbsoluteValue : DiagGroup<"absolute-value">;
22 def AddressOfTemporary : DiagGroup<"address-of-temporary">;
23 def : DiagGroup<"aggregate-return">;
24 def GNUAlignofExpression : DiagGroup<"gnu-alignof-expression">;
25 def AmbigMemberTemplate : DiagGroup<"ambiguous-member-template">;
26 def GNUAnonymousStruct : DiagGroup<"gnu-anonymous-struct">;
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/external/llvm/lib/Target/PowerPC/
DPPCSchedule.td13 def IIC_IntSimple : InstrItinClass;
14 def IIC_IntGeneral : InstrItinClass;
15 def IIC_IntCompare : InstrItinClass;
16 def IIC_IntISEL : InstrItinClass;
17 def IIC_IntDivD : InstrItinClass;
18 def IIC_IntDivW : InstrItinClass;
19 def IIC_IntMFFS : InstrItinClass;
20 def IIC_IntMFVSCR : InstrItinClass;
21 def IIC_IntMTFSB0 : InstrItinClass;
22 def IIC_IntMTSRD : InstrItinClass;
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/external/clang/include/clang/AST/
DCommentHTMLNamedCharacterReferences.td15 def : NCR<"copy", 0x000A9>;
16 def : NCR<"COPY", 0x000A9>;
17 def : NCR<"trade", 0x02122>;
18 def : NCR<"TRADE", 0x02122>;
19 def : NCR<"reg", 0x000AE>;
20 def : NCR<"REG", 0x000AE>;
21 def : NCR<"lt", 0x0003C>;
22 def : NCR<"Lt", 0x0003C>;
23 def : NCR<"LT", 0x0003C>;
24 def : NCR<"gt", 0x0003E>;
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DCommentCommands.td51 def Begin : Command<name> {
56 def End : Command<endCommandName> {
84 def B : InlineCommand<"b">;
85 def C : InlineCommand<"c">;
86 def P : InlineCommand<"p">;
87 def A : InlineCommand<"a">;
88 def E : InlineCommand<"e">;
89 def Em : InlineCommand<"em">;
95 def Brief : BlockCommand<"brief"> { let IsBriefCommand = 1; }
96 def Short : BlockCommand<"short"> { let IsBriefCommand = 1; }
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/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsics.td159 def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>;
160 def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>;
161 def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>;
162 def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>;
163 def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>;
164 def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>;
165 def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>;
166 def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>;
168 def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>;
169 def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>;
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DHexagonIntrinsicsV4.td17 def : T_PP_pat <M4_vrmpyeh_s0, int_hexagon_M4_vrmpyeh_s0>;
18 def : T_PP_pat <M4_vrmpyeh_s1, int_hexagon_M4_vrmpyeh_s1>;
21 def : T_PP_pat <M4_vrmpyoh_s0, int_hexagon_M4_vrmpyoh_s0>;
22 def : T_PP_pat <M4_vrmpyoh_s1, int_hexagon_M4_vrmpyoh_s1>;
25 def : T_PPP_pat <M4_vrmpyeh_acc_s0, int_hexagon_M4_vrmpyeh_acc_s0>;
26 def : T_PPP_pat <M4_vrmpyeh_acc_s1, int_hexagon_M4_vrmpyeh_acc_s1>;
29 def : T_PPP_pat <M4_vrmpyoh_acc_s0, int_hexagon_M4_vrmpyoh_acc_s0>;
30 def : T_PPP_pat <M4_vrmpyoh_acc_s1, int_hexagon_M4_vrmpyoh_acc_s1>;
34 def : T_RR_pat <M2_vmpy2su_s0, int_hexagon_M2_vmpy2su_s0>;
35 def : T_RR_pat <M2_vmpy2su_s1, int_hexagon_M2_vmpy2su_s1>;
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DHexagonIntrinsicsV5.td13 def : T_PP_pat <M5_vrmpybsu, int_hexagon_M5_vrmpybsu>;
14 def : T_PP_pat <M5_vrmpybuu, int_hexagon_M5_vrmpybuu>;
16 def : T_PP_pat <M5_vdmpybsu, int_hexagon_M5_vdmpybsu>;
18 def : T_PPP_pat <M5_vrmacbsu, int_hexagon_M5_vrmacbsu>;
19 def : T_PPP_pat <M5_vrmacbuu, int_hexagon_M5_vrmacbuu>;
21 def : T_PPP_pat <M5_vdmacbsu, int_hexagon_M5_vdmacbsu>;
25 def : T_RR_pat <M5_vmpybsu, int_hexagon_M5_vmpybsu>;
26 def : T_RR_pat <M5_vmpybuu, int_hexagon_M5_vmpybuu>;
29 def : T_PRR_pat <M5_vmacbsu, int_hexagon_M5_vmacbsu>;
30 def : T_PRR_pat <M5_vmacbuu, int_hexagon_M5_vmacbuu>;
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/external/llvm/lib/Target/AVR/
DAVR.td53 def FeatureSRAM : SubtargetFeature<"sram", "m_hasSRAM", "true",
57 def FeatureJMPCALL : SubtargetFeature<"jmpcall", "m_hasJMPCALL", "true",
63 def FeatureIJMPCALL : SubtargetFeature<"ijmpcall", "m_hasIJMPCALL",
69 def FeatureEIJMPCALL : SubtargetFeature<"eijmpcall", "m_hasEIJMPCALL",
74 def FeatureADDSUBIW : SubtargetFeature<"addsubiw", "m_hasADDSUBIW",
79 def FeatureSmallStack : SubtargetFeature<"smallstack", "m_hasSmallStack",
84 def FeatureMOVW : SubtargetFeature<"movw", "m_hasMOVW", "true",
89 def FeatureLPM : SubtargetFeature<"lpm", "m_hasLPM", "true",
93 def FeatureLPMX : SubtargetFeature<"lpmx", "m_hasLPMX", "true",
98 def FeatureELPM : SubtargetFeature<"elpm", "m_hasELPM", "true",
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/external/llvm/lib/Target/Mips/
DMipsSchedule.td13 def ALU : FuncUnit;
14 def IMULDIV : FuncUnit;
20 def IIM16Alu : InstrItinClass;
21 def IIPseudo : InstrItinClass;
23 def II_ABS : InstrItinClass;
24 def II_ADDI : InstrItinClass;
25 def II_ADDIU : InstrItinClass;
26 def II_ADDU : InstrItinClass;
27 def II_ADD_D : InstrItinClass;
28 def II_ADD_S : InstrItinClass;
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DMipsRegisterInfo.td14 def sub_32 : SubRegIndex<32>;
15 def sub_64 : SubRegIndex<64>;
16 def sub_lo : SubRegIndex<32>;
17 def sub_hi : SubRegIndex<32, 32>;
18 def sub_dsp16_19 : SubRegIndex<4, 16>;
19 def sub_dsp20 : SubRegIndex<1, 20>;
20 def sub_dsp21 : SubRegIndex<1, 21>;
21 def sub_dsp22 : SubRegIndex<1, 22>;
22 def sub_dsp23 : SubRegIndex<1, 23>;
88 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
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/external/llvm/test/TableGen/
DNestedForeach.td14 def S#R#M#P : Droid<S, R, M, P>;
20 // CHECK: def C2D0
21 // CHECK: def C2D2
22 // CHECK: def C2D4
23 // CHECK: def C2P0
24 // CHECK: def C2P2
25 // CHECK: def C2P4
26 // CHECK: def C2Q0
27 // CHECK: def C2Q2
28 // CHECK: def C2Q4
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/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td25 def sub_even : SubRegIndex<32>;
26 def sub_odd : SubRegIndex<32, 32>;
27 def sub_even64 : SubRegIndex<64>;
28 def sub_odd64 : SubRegIndex<64, 64>;
59 def ICC : SparcCtrlReg<0, "ICC">; // This represents icc and xcc in 64-bit code.
61 def FCC#I : SparcCtrlReg<I, "FCC"#I>;
63 def FSR : SparcCtrlReg<0, "FSR">; // Floating-point state register.
66 def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>;
68 def ASR1 : SparcCtrlReg<1, "ASR1">;
69 def ASR2 : SparcCtrlReg<2, "ASR2">;
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/external/llvm/include/llvm/IR/
DIntrinsicsMips.td16 def mips_v2q15_ty: LLVMType<v2i16>;
17 def mips_v4q7_ty: LLVMType<v4i8>;
18 def mips_q31_ty: LLVMType<i32>;
28 def int_mips_addu_qb : GCCBuiltin<"__builtin_mips_addu_qb">,
31 def int_mips_addu_s_qb : GCCBuiltin<"__builtin_mips_addu_s_qb">,
34 def int_mips_subu_qb : GCCBuiltin<"__builtin_mips_subu_qb">,
36 def int_mips_subu_s_qb : GCCBuiltin<"__builtin_mips_subu_s_qb">,
39 def int_mips_addq_ph : GCCBuiltin<"__builtin_mips_addq_ph">,
42 def int_mips_addq_s_ph : GCCBuiltin<"__builtin_mips_addq_s_ph">,
45 def int_mips_subq_ph : GCCBuiltin<"__builtin_mips_subq_ph">,
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DIntrinsicsPowerPC.td21 def int_ppc_dcba : Intrinsic<[], [llvm_ptr_ty], []>;
22 def int_ppc_dcbf : Intrinsic<[], [llvm_ptr_ty], []>;
23 def int_ppc_dcbi : Intrinsic<[], [llvm_ptr_ty], []>;
24 def int_ppc_dcbst : Intrinsic<[], [llvm_ptr_ty], []>;
25 def int_ppc_dcbt : Intrinsic<[], [llvm_ptr_ty],
27 def int_ppc_dcbtst: Intrinsic<[], [llvm_ptr_ty],
29 def int_ppc_dcbz : Intrinsic<[], [llvm_ptr_ty], []>;
30 def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>;
33 def int_ppc_sync : Intrinsic<[], [], []>;
35 def int_ppc_lwsync : Intrinsic<[], [], []>;
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DIntrinsicsAArch64.td16 def int_aarch64_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
19 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
20 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
21 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
22 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
24 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
25 def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
26 def int_aarch64_stxp : Intrinsic<[llvm_i32_ty],
28 def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
31 def int_aarch64_clrex : Intrinsic<[]>;
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DIntrinsicsHexagon.td651 def int_hexagon_SI_to_SXTHI_asrh :
656 def int_hexagon_brev_ldd :
661 def int_hexagon_brev_ldw :
666 def int_hexagon_brev_ldh :
671 def int_hexagon_brev_lduh :
676 def int_hexagon_brev_ldb :
681 def int_hexagon_brev_ldub :
686 def int_hexagon_circ_ldd :
691 def int_hexagon_circ_ldw :
696 def int_hexagon_circ_ldh :
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/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td23 def sub_32 : SubRegIndex<32>;
25 def bsub : SubRegIndex<8>;
26 def hsub : SubRegIndex<16>;
27 def ssub : SubRegIndex<32>;
28 def dsub : SubRegIndex<32>;
29 def sube32 : SubRegIndex<32>;
30 def subo32 : SubRegIndex<32>;
31 def qhisub : SubRegIndex<64>;
32 def qsub : SubRegIndex<64>;
33 def sube64 : SubRegIndex<64>;
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DAArch64SchedA57.td24 def CortexA57Model : SchedMachineModel {
40 def A57UnitB : ProcResource<1>; // Type B micro-ops
41 def A57UnitI : ProcResource<2>; // Type I micro-ops
42 def A57UnitM : ProcResource<1>; // Type M micro-ops
43 def A57UnitL : ProcResource<1>; // Type L micro-ops
44 def A57UnitS : ProcResource<1>; // Type S micro-ops
45 def A57UnitX : ProcResource<1>; // Type X micro-ops
46 def A57UnitW : ProcResource<1>; // Type W micro-ops
48 def A57UnitV : ProcResGroup<[A57UnitX, A57UnitW]>; // Type V micro-ops
70 def : SchedAlias<WriteImm, A57Write_1cyc_1I>;
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/external/llvm/lib/Target/AMDGPU/
DSIIntrinsics.td17 def int_SI_tid : Intrinsic <[llvm_i32_ty], [], [IntrNoMem]>;
18 def int_SI_packf16 : Intrinsic <[llvm_i32_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
19 …def int_SI_export : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_t…
20 def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
21 …def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_anyint_ty, llvm_i16_ty, llvm_i32_ty],…
24 def int_SI_tbuffer_store : Intrinsic <
42 def int_SI_buffer_load_dword : Intrinsic <
55 def int_SI_sendmsg : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
89 def int_SI_image_sample : SampleRaw;
90 def int_SI_image_sample_cl : SampleRaw;
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/external/mesa3d/src/gallium/drivers/radeon/
DSIInstructions.td10 def isSI : Predicate<"Subtarget.device()"
16 def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>;
17 def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>;
18 def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>;
19 def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>;
20 def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32", []>;
21 def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>;
22 def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>;
23 def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>;
24 def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>;
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DAMDILIntrinsics.td69 def int_AMDIL_fabs : GCCBuiltin<"__amdil_fabs">, UnaryIntFloat;
70 def int_AMDIL_abs : GCCBuiltin<"__amdil_abs">, UnaryIntInt;
72 def int_AMDIL_bit_extract_i32 : GCCBuiltin<"__amdil_ibit_extract">,
74 def int_AMDIL_bit_extract_u32 : GCCBuiltin<"__amdil_ubit_extract">,
76 def int_AMDIL_bit_reverse_u32 : GCCBuiltin<"__amdil_ubit_reverse">,
78 def int_AMDIL_bit_count_i32 : GCCBuiltin<"__amdil_count_bits">,
80 def int_AMDIL_bit_find_first_lo : GCCBuiltin<"__amdil_ffb_lo">,
82 def int_AMDIL_bit_find_first_hi : GCCBuiltin<"__amdil_ffb_hi">,
84 def int_AMDIL_bit_find_first_sgn : GCCBuiltin<"__amdil_ffb_signed">,
86 def int_AMDIL_media_bitalign : GCCBuiltin<"__amdil_bitalign">,
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