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Searched refs:fcvtau (Results 1 – 25 of 28) sorted by relevance

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/external/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s104 fcvtau h12, h13
105 fcvtau s12, s13
106 fcvtau d21, d14
Darm64-fp-encoding.s272 fcvtau w1, h2
273 fcvtau w1, s2
274 fcvtau w1, d2
275 fcvtau x1, h2
276 fcvtau x1, s2
277 fcvtau x1, d2
279 ; FP16: fcvtau w1, h2 ; encoding: [0x41,0x00,0xe5,0x1e]
281 ; NO-FP16-NEXT: fcvtau w1, h2
282 ; CHECK: fcvtau w1, s2 ; encoding: [0x41,0x00,0x25,0x1e]
283 ; CHECK: fcvtau w1, d2 ; encoding: [0x41,0x00,0x65,0x1e]
[all …]
Dneon-simd-misc.s658 fcvtau v4.4h, v0.4h
659 fcvtau v6.8h, v8.8h
660 fcvtau v6.4s, v8.4s
661 fcvtau v6.2d, v8.2d
662 fcvtau v4.2s, v0.2s
Dfullfp16-neon-neg.s232 fcvtau h12, h13
366 fcvtau v4.4h, v0.4h
368 fcvtau v6.8h, v8.8h
Darm64-advsimd.s792 fcvtau.2s v0, v0
793 fcvtau.4s v0, v0
794 fcvtau.2d v0, v0
795 fcvtau s0, s0
796 fcvtau d0, d0 define
798 ; CHECK: fcvtau.2s v0, v0 ; encoding: [0x00,0xc8,0x21,0x2e]
799 ; CHECK: fcvtau.4s v0, v0 ; encoding: [0x00,0xc8,0x21,0x6e]
800 ; CHECK: fcvtau.2d v0, v0 ; encoding: [0x00,0xc8,0x61,0x6e]
801 ; CHECK: fcvtau s0, s0 ; encoding: [0x00,0xc8,0x21,0x7e]
802 ; CHECK: fcvtau d0, d0 ; encoding: [0x00,0xc8,0x61,0x7e]
Dneon-diagnostics.s5936 fcvtau v0.16b, v31.16b
5937 fcvtau v2.8h, v4.8h
5938 fcvtau v1.8b, v9.8b
5939 fcvtau v13.4h, v21.4h
7192 fcvtau s0, d0
7193 fcvtau d0, s0 define
Dbasic-a64-instructions.s2115 fcvtau w29, s30
2116 fcvtau xzr, s0
2169 fcvtau w29, d30
2170 fcvtau xzr, d0
/external/llvm/test/CodeGen/AArch64/
Darm64-cvt.ll48 ;CHECK: fcvtau w0, s0
50 %tmp3 = call i32 @llvm.aarch64.neon.fcvtau.i32.f32(float %A)
56 ;CHECK: fcvtau x0, s0
58 %tmp3 = call i64 @llvm.aarch64.neon.fcvtau.i64.f32(float %A)
64 ;CHECK: fcvtau w0, d0
66 %tmp3 = call i32 @llvm.aarch64.neon.fcvtau.i32.f64(double %A)
72 ;CHECK: fcvtau x0, d0
74 %tmp3 = call i64 @llvm.aarch64.neon.fcvtau.i64.f64(double %A)
78 declare i32 @llvm.aarch64.neon.fcvtau.i32.f32(float) nounwind readnone
79 declare i64 @llvm.aarch64.neon.fcvtau.i64.f32(float) nounwind readnone
[all …]
Dround-conv.ll284 ; CHECK: fcvtau w0, s0
294 ; CHECK: fcvtau x0, s0
304 ; CHECK: fcvtau w0, d0
314 ; CHECK: fcvtau x0, d0
Darm64-vcvt.ll37 ;CHECK: fcvtau.2s v0, v0
39 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float> %A)
46 ;CHECK: fcvtau.4s v0, v0
48 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float> %A)
55 ;CHECK: fcvtau.2d v0, v0
57 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double> %A)
61 declare <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float>) nounwind readnone
62 declare <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float>) nounwind readnone
63 declare <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double>) nounwind readnone
/external/vixl/doc/
Dchangelog.md93 `frinta`, `fcvtau` and `fcvtas`.
Dsupported-instructions.md1906 void fcvtau(const Register& rd, const VRegister& vn)
1913 void fcvtau(const VRegister& vd, const VRegister& vn)
/external/v8/test/cctest/
Dtest-disasm-arm64.cc1513 COMPARE(fcvtau(w8, s9), "fcvtau w8, s9"); in TEST_()
1514 COMPARE(fcvtau(x10, s11), "fcvtau x10, s11"); in TEST_()
1515 COMPARE(fcvtau(w12, d13), "fcvtau w12, d13"); in TEST_()
1516 COMPARE(fcvtau(x14, d15), "fcvtau x14, d15"); in TEST_()
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt1739 # FP16: fcvtau w29, h30
1740 # FP16: fcvtau xzr, h0
1793 # CHECK: fcvtau w29, s30
1794 # CHECK: fcvtau xzr, s0
1847 # CHECK: fcvtau w29, d30
1848 # CHECK: fcvtau xzr, d0
Dneon-instructions.txt2552 # CHECK: fcvtau s12, s13
2553 # CHECK: fcvtau d21, d14
Darm64-advsimd.txt471 # CHECK: fcvtau.2s v0, v0
/external/vixl/test/
Dtest-simulator-a64.cc2551 DEFINE_TEST_FP_TO_INT(fcvtau, FPToU, Conversions) in DEFINE_TEST_FP_TO_INT()
3982 DEFINE_TEST_NEON_2SAME_FP(fcvtau, Conversions) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
4028 DEFINE_TEST_NEON_2SAME_FP_SCALAR(fcvtau, Conversions)
Dtest-disasm-a64.cc2437 COMPARE(fcvtau(w8, s9), "fcvtau w8, s9"); in TEST()
2438 COMPARE(fcvtau(x10, s11), "fcvtau x10, s11"); in TEST()
2439 COMPARE(fcvtau(w12, d13), "fcvtau w12, d13"); in TEST()
2440 COMPARE(fcvtau(x14, d15), "fcvtau x14, d15"); in TEST()
/external/v8/src/arm64/
Dmacro-assembler-arm64-inl.h611 fcvtau(rd, fn); in Fcvtau()
Dassembler-arm64.h1582 void fcvtau(const Register& rd, const FPRegister& fn);
Dassembler-arm64.cc1980 void Assembler::fcvtau(const Register& rd, const FPRegister& fn) { in fcvtau() function in v8::internal::Assembler
/external/vixl/src/vixl/a64/
Dmacro-assembler-a64.h1231 fcvtau(rd, vn); in Fcvtau()
2261 V(fcvtau, Fcvtau) \
Dassembler-a64.h2195 void fcvtau(const Register& rd, const VRegister& vn);
2201 void fcvtau(const VRegister& vd, const VRegister& vn);
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp26693 fcvtau d21, d10 14a0e8bd770a848aa7cd15a0503d7245 9464c2f8f35d8a220add60f775cfc483 0000000000000…
26695 fcvtau s21, s10 0c42673f7db2453da00bca34047f4cd3 180da2db6b8470a941cff4e0b9dacf15 0000000000000…
26697 fcvtau v10.2d, v21.2d b1941fee5d41f94734bd9667b87b1fa2 b93b2194ec09c9efcbff7271684d9052 0000000…
26699 fcvtau v10.4s, v21.4s 8458e704930ca741c5f2c39392c13af0 e8bc129622a97c05b293b2d99cebfbee 0000000…
26701 fcvtau v10.2s, v21.2s 8491c2821e134e2b54aa52b691549fbe a39174de0e6589eaf68ab21956b50fea 0000000…
26703 fcvtau w21, s10 b23dae67ff55ee04e1e742d0b6324e0b edb9486eaf3dee9f98e5753095aacd45 b23dae67ff55e…
26705 fcvtau x21, s10 c4358e460630ae2398a3f91e5acb3400 cd108f59527580861e3de18f437b6141 c4358e460630a…
26707 fcvtau w21, d10 28044565123ec677f5c43ee5a517451a 59175a806b15ca511db9a52e745b6d86 28044565123ec…
26709 fcvtau x21, d10 1a276dccd468399aaf494582758fff94 d253f7cd99b1cecdd9788a848a46820a 1a276dccd4683…
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2436 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2708 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>;
3268 defm FCVTAU : SIMDFPTwoScalar< 1, 0, 0b11100, "fcvtau">;

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