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Searched refs:fcvtms (Results 1 – 25 of 27) sorted by relevance

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/external/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s117 fcvtms h22, h13
118 fcvtms s22, s13
119 fcvtms d21, d14
Darm64-fp-encoding.s290 fcvtms w1, h2
291 fcvtms w1, s2
292 fcvtms w1, d2
293 fcvtms x1, h2
294 fcvtms x1, s2
295 fcvtms x1, d2
297 ; FP16: fcvtms w1, h2 ; encoding: [0x41,0x00,0xf0,0x1e]
299 ; NO-FP16-NEXT: fcvtms w1, h2
300 ; CHECK: fcvtms w1, s2 ; encoding: [0x41,0x00,0x30,0x1e]
301 ; CHECK: fcvtms w1, d2 ; encoding: [0x41,0x00,0x70,0x1e]
[all …]
Dneon-simd-misc.s597 fcvtms v4.4h, v0.4h
598 fcvtms v6.8h, v8.8h
599 fcvtms v6.4s, v8.4s
600 fcvtms v6.2d, v8.2d
601 fcvtms v4.2s, v0.2s
Dfullfp16-neon-neg.s234 fcvtms h22, h13
346 fcvtms v4.4h, v0.4h
348 fcvtms v6.8h, v8.8h
Darm64-advsimd.s814 fcvtms.2s v0, v0
815 fcvtms.4s v0, v0
816 fcvtms.2d v0, v0
817 fcvtms s0, s0
818 fcvtms d0, d0 define
820 ; CHECK: fcvtms.2s v0, v0 ; encoding: [0x00,0xb8,0x21,0x0e]
821 ; CHECK: fcvtms.4s v0, v0 ; encoding: [0x00,0xb8,0x21,0x4e]
822 ; CHECK: fcvtms.2d v0, v0 ; encoding: [0x00,0xb8,0x61,0x4e]
823 ; CHECK: fcvtms s0, s0 ; encoding: [0x00,0xb8,0x21,0x5e]
824 ; CHECK: fcvtms d0, d0 ; encoding: [0x00,0xb8,0x61,0x5e]
Dneon-diagnostics.s5911 fcvtms v0.16b, v31.16b
5912 fcvtms v2.8h, v4.8h
5913 fcvtms v1.8b, v9.8b
5914 fcvtms v13.4h, v21.4h
7207 fcvtms s0, d0
7208 fcvtms d0, s0 define
Dbasic-a64-instructions.s2086 fcvtms w2, s3
2087 fcvtms x4, s5
2140 fcvtms w2, d3
2141 fcvtms x4, d5
/external/llvm/test/CodeGen/AArch64/
Darm64-cvt.ll88 ;CHECK: fcvtms w0, s0
90 %tmp3 = call i32 @llvm.aarch64.neon.fcvtms.i32.f32(float %A)
96 ;CHECK: fcvtms x0, s0
98 %tmp3 = call i64 @llvm.aarch64.neon.fcvtms.i64.f32(float %A)
104 ;CHECK: fcvtms w0, d0
106 %tmp3 = call i32 @llvm.aarch64.neon.fcvtms.i32.f64(double %A)
112 ;CHECK: fcvtms x0, d0
114 %tmp3 = call i64 @llvm.aarch64.neon.fcvtms.i64.f64(double %A)
118 declare i32 @llvm.aarch64.neon.fcvtms.i32.f32(float) nounwind readnone
119 declare i64 @llvm.aarch64.neon.fcvtms.i64.f32(float) nounwind readnone
[all …]
Dround-conv.ll4 ; CHECK: fcvtms w0, s0
14 ; CHECK: fcvtms x0, s0
24 ; CHECK: fcvtms w0, d0
34 ; CHECK: fcvtms x0, d0
Darm64-vcvt.ll68 ;CHECK: fcvtms.2s v0, v0
70 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtms.v2i32.v2f32(<2 x float> %A)
77 ;CHECK: fcvtms.4s v0, v0
79 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtms.v4i32.v4f32(<4 x float> %A)
86 ;CHECK: fcvtms.2d v0, v0
88 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double> %A)
92 declare <2 x i32> @llvm.aarch64.neon.fcvtms.v2i32.v2f32(<2 x float>) nounwind readnone
93 declare <4 x i32> @llvm.aarch64.neon.fcvtms.v4i32.v4f32(<4 x float>) nounwind readnone
94 declare <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double>) nounwind readnone
/external/v8/test/cctest/
Dtest-disasm-arm64.cc1555 COMPARE(fcvtms(w0, s1), "fcvtms w0, s1"); in TEST_()
1556 COMPARE(fcvtms(x2, s3), "fcvtms x2, s3"); in TEST_()
1557 COMPARE(fcvtms(w4, d5), "fcvtms w4, d5"); in TEST_()
1558 COMPARE(fcvtms(x6, d7), "fcvtms x6, d7"); in TEST_()
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt1710 # FP16: fcvtms w2, h3
1711 # FP16: fcvtms x4, h5
1764 # CHECK: fcvtms w2, s3
1765 # CHECK: fcvtms x4, s5
1818 # CHECK: fcvtms w2, d3
1819 # CHECK: fcvtms x4, d5
Dneon-instructions.txt2561 # CHECK: fcvtms s22, s13
2562 # CHECK: fcvtms d21, d14
Darm64-advsimd.txt472 # CHECK: fcvtms.2s v0, v0
/external/vixl/test/
Dtest-simulator-a64.cc2552 DEFINE_TEST_FP_TO_INT(fcvtms, FPToS, Conversions) in DEFINE_TEST_FP_TO_INT()
3952 DEFINE_TEST_NEON_2SAME_FP(fcvtms, Conversions) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
4006 DEFINE_TEST_NEON_2SAME_FP_SCALAR(fcvtms, Conversions) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
Dtest-disasm-a64.cc2499 COMPARE(fcvtms(w0, s1), "fcvtms w0, s1"); in TEST()
2500 COMPARE(fcvtms(x2, s3), "fcvtms x2, s3"); in TEST()
2501 COMPARE(fcvtms(w4, d5), "fcvtms w4, d5"); in TEST()
2502 COMPARE(fcvtms(x6, d7), "fcvtms x6, d7"); in TEST()
/external/v8/src/arm64/
Dmacro-assembler-arm64-inl.h618 fcvtms(rd, fn); in Fcvtms()
Dassembler-arm64.h1591 void fcvtms(const Register& rd, const FPRegister& fn);
Dassembler-arm64.cc1995 void Assembler::fcvtms(const Register& rd, const FPRegister& fn) { in fcvtms() function in v8::internal::Assembler
/external/vixl/src/vixl/a64/
Dmacro-assembler-a64.h1237 fcvtms(rd, vn); in Fcvtms()
2262 V(fcvtms, Fcvtms) \
Dassembler-a64.h2204 void fcvtms(const Register& rd, const VRegister& vn);
2210 void fcvtms(const VRegister& vd, const VRegister& vn);
Dassembler-a64.cc2865 V(fcvtms, NEON_FCVTMS, FCVTMS) \
/external/vixl/doc/
Dsupported-instructions.md1934 void fcvtms(const Register& rd, const VRegister& vn)
1941 void fcvtms(const VRegister& vd, const VRegister& vn)
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp26710 fcvtms d10, d21 18681caa09d8034ac0e161327f6b0c45 f8942473a90de53c4f21d965dc104153 0000000000000…
26712 fcvtms s10, s21 fea88f1cfbcb9c44261baab3b7c464ee f6bc1a1c97411fde476610efebad0456 0000000000000…
26714 fcvtms v10.2d, v21.2d f1bbf356235a0e8e6b39358bf5c9e677 6198636c1cf292b07d6ee9b05fd55119 7ffffff…
26716 fcvtms v10.4s, v21.4s 3a27fd64351d3fb2f03a63a93988289b ef079e50c961a9cdd980a8f73cea65c6 8000000…
26718 fcvtms v10.2s, v21.2s b9cf9a622125fc220836beec7ec87c5d 85d9821f0ac40979e945797022bf1865 0000000…
26720 fcvtms w21, s10 502a47fc6f46e986d48fd6f985127d94 4c950ba8ec1d70bd5f21d73e98445c2e 502a47fc6f46e…
26722 fcvtms x21, s10 b518a51db2c16ffa3e8cef1e52c7676b 41c3a69823b2cff1d28096033415e976 b518a51db2c16…
26724 fcvtms w21, d10 e89ab5c6ea988f7e452c0959e5e83be1 636652f0b18328144363b7c0f531c03e e89ab5c6ea988…
26726 fcvtms x21, d10 e8af77f618cb4910e97025ad3d75f9f6 b27b10af938f7b27b1c93974dc99e185 e8af77f618cb4…
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2437 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;
2725 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>;
3269 defm FCVTMS : SIMDFPTwoScalar< 0, 0, 0b11011, "fcvtms">;

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