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Searched refs:fcvtnu (Results 1 – 25 of 26) sorted by relevance

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/external/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s156 fcvtnu h12, h13
157 fcvtnu s12, s13
158 fcvtnu d21, d14
Darm64-fp-encoding.s344 fcvtnu w1, h2
345 fcvtnu w1, s2
346 fcvtnu w1, d2
347 fcvtnu x1, h2
348 fcvtnu x1, s2
349 fcvtnu x1, d2
351 ; FP16: fcvtnu w1, h2 ; encoding: [0x41,0x00,0xe1,0x1e]
353 ; NO-FP16-NEXT: fcvtnu w1, h2
354 ; CHECK: fcvtnu w1, s2 ; encoding: [0x41,0x00,0x21,0x1e]
355 ; CHECK: fcvtnu w1, d2 ; encoding: [0x41,0x00,0x61,0x1e]
[all …]
Dneon-simd-misc.s561 fcvtnu v4.4h, v0.4h
562 fcvtnu v6.8h, v8.8h
563 fcvtnu v6.4s, v8.4s
564 fcvtnu v6.2d, v8.2d
565 fcvtnu v4.2s, v0.2s
Dfullfp16-neon-neg.s240 fcvtnu h12, h13
334 fcvtnu v4.4h, v0.4h
336 fcvtnu v6.8h, v8.8h
Darm64-advsimd.s850 fcvtnu.2s v0, v0
851 fcvtnu.4s v0, v0
852 fcvtnu.2d v0, v0
853 fcvtnu s0, s0
854 fcvtnu d0, d0 define
856 ; CHECK: fcvtnu.2s v0, v0 ; encoding: [0x00,0xa8,0x21,0x2e]
857 ; CHECK: fcvtnu.4s v0, v0 ; encoding: [0x00,0xa8,0x21,0x6e]
858 ; CHECK: fcvtnu.2d v0, v0 ; encoding: [0x00,0xa8,0x61,0x6e]
859 ; CHECK: fcvtnu s0, s0 ; encoding: [0x00,0xa8,0x21,0x7e]
860 ; CHECK: fcvtnu d0, d0 ; encoding: [0x00,0xa8,0x61,0x7e]
Dneon-diagnostics.s5896 fcvtnu v0.16b, v31.16b
5897 fcvtnu v2.8h, v4.8h
5898 fcvtnu v1.8b, v9.8b
5899 fcvtnu v13.4h, v21.4h
7252 fcvtnu s0, d0
7253 fcvtnu d0, s0 define
Dbasic-a64-instructions.s2070 fcvtnu wzr, s12
2071 fcvtnu x0, s0
2124 fcvtnu wzr, d12
2125 fcvtnu x0, d0
/external/llvm/test/CodeGen/AArch64/
Darm64-cvt.ll208 ;CHECK: fcvtnu w0, s0
210 %tmp3 = call i32 @llvm.aarch64.neon.fcvtnu.i32.f32(float %A)
216 ;CHECK: fcvtnu x0, s0
218 %tmp3 = call i64 @llvm.aarch64.neon.fcvtnu.i64.f32(float %A)
224 ;CHECK: fcvtnu w0, d0
226 %tmp3 = call i32 @llvm.aarch64.neon.fcvtnu.i32.f64(double %A)
232 ;CHECK: fcvtnu x0, d0
234 %tmp3 = call i64 @llvm.aarch64.neon.fcvtnu.i64.f64(double %A)
238 declare i32 @llvm.aarch64.neon.fcvtnu.i32.f32(float) nounwind readnone
239 declare i64 @llvm.aarch64.neon.fcvtnu.i64.f32(float) nounwind readnone
[all …]
Darm64-vcvt.ll223 ;CHECK: fcvtnu.2s v0, v0
225 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtnu.v2i32.v2f32(<2 x float> %A)
232 ;CHECK: fcvtnu.4s v0, v0
234 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtnu.v4i32.v4f32(<4 x float> %A)
241 ;CHECK: fcvtnu.2d v0, v0
243 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtnu.v2i64.v2f64(<2 x double> %A)
247 declare <2 x i32> @llvm.aarch64.neon.fcvtnu.v2i32.v2f32(<2 x float>) nounwind readnone
248 declare <4 x i32> @llvm.aarch64.neon.fcvtnu.v4i32.v4f32(<4 x float>) nounwind readnone
249 declare <2 x i64> @llvm.aarch64.neon.fcvtnu.v2i64.v2f64(<2 x double>) nounwind readnone
/external/v8/test/cctest/
Dtest-disasm-arm64.cc1521 COMPARE(fcvtnu(w8, s9), "fcvtnu w8, s9"); in TEST_()
1522 COMPARE(fcvtnu(x10, s11), "fcvtnu x10, s11"); in TEST_()
1523 COMPARE(fcvtnu(w12, d13), "fcvtnu w12, d13"); in TEST_()
1524 COMPARE(fcvtnu(x14, d15), "fcvtnu x14, d15"); in TEST_()
Dtest-assembler-arm64.cc7376 TEST(fcvtnu) { in TEST() argument
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt1694 # FP16: fcvtnu wzr, h12
1695 # FP16: fcvtnu x0, h0
1748 # CHECK: fcvtnu wzr, s12
1749 # CHECK: fcvtnu x0, s0
1802 # CHECK: fcvtnu wzr, d12
1803 # CHECK: fcvtnu x0, d0
Darm64-advsimd.txt475 # CHECK: fcvtnu.2s v0, v0
587 # 'bic.4h' should be selected over "fcvtnu.2s v0, v1, #0"
604 # "bic.8h" should be selected over "fcvtnu.4s v0, v1, #0"
Dneon-instructions.txt2591 # CHECK: fcvtnu s12, s13
2592 # CHECK: fcvtnu d21, d14
/external/vixl/test/
Dtest-simulator-a64.cc2555 DEFINE_TEST_FP_TO_INT(fcvtnu, FPToU, Conversions) in DEFINE_TEST_FP_TO_INT()
3980 DEFINE_TEST_NEON_2SAME_FP(fcvtnu, Conversions) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
4026 DEFINE_TEST_NEON_2SAME_FP_SCALAR(fcvtnu, Conversions)
Dtest-disasm-a64.cc2445 COMPARE(fcvtnu(w8, s9), "fcvtnu w8, s9"); in TEST()
2446 COMPARE(fcvtnu(x10, s11), "fcvtnu x10, s11"); in TEST()
2447 COMPARE(fcvtnu(w12, d13), "fcvtnu w12, d13"); in TEST()
2448 COMPARE(fcvtnu(x14, d15), "fcvtnu x14, d15"); in TEST()
/external/v8/src/arm64/
Dmacro-assembler-arm64-inl.h639 fcvtnu(rd, fn); in Fcvtnu()
Dassembler-arm64.h1594 void fcvtnu(const Register& rd, const FPRegister& fn);
Dassembler-arm64.cc2000 void Assembler::fcvtnu(const Register& rd, const FPRegister& fn) { in fcvtnu() function in v8::internal::Assembler
/external/vixl/src/vixl/a64/
Dmacro-assembler-a64.h1255 fcvtnu(rd, vn); in Fcvtnu()
2265 V(fcvtnu, Fcvtnu) \
Dassembler-a64.h2219 void fcvtnu(const Register& rd, const VRegister& vn);
2225 void fcvtnu(const VRegister& rd, const VRegister& vn);
Dassembler-a64.cc2860 V(fcvtnu, NEON_FCVTNU, FCVTNU) \
/external/vixl/doc/
Dsupported-instructions.md1990 void fcvtnu(const Register& rd, const VRegister& vn)
1997 void fcvtnu(const VRegister& rd, const VRegister& vn)
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp26729 fcvtnu d21, d10 19b4f6cd19538fbaf8f8a2c603e15a91 cf455e005761bbf5e2c923c32dd3ec50 0000000000000…
26731 fcvtnu s21, s10 bbda94f04d0ae894c6f4e274691a7fd6 b11b67e230a21d7e6a9739021197e4f6 0000000000000…
26734 fcvtnu v10.2d, v21.2d aa14631bf69d5bfdb214a3b9153f0e39 40e502acde9ef977706a31b89b27a69b 0000000…
26736 fcvtnu v10.4s, v21.4s e761634d150be7f6bb57e697054f06bd 7ca32f5d61564ee0f3400ae6cb833141 fffffff…
26738 fcvtnu v10.2s, v21.2s 71c19586a9558c7ee2beaa0b3c4b685f 6654edf5bac91db8f319c48ca0aa86e5 0000000…
26740 fcvtnu w21, s10 4936f8c7b27b4c952749f017b8323322 fdf93c75e8f8660072f660a91a9da489 4936f8c7b27b4…
26742 fcvtnu x21, s10 6ebd8d10327c243d89f7b7bb79056703 42911dddece227b76dd6dd3d3a5b8c2d 6ebd8d10327c2…
26744 fcvtnu w21, d10 351c902cc58863dde6ba3c4900e43dd0 8b040737889bb1293e9c083e2671f83c 351c902cc5886…
26746 fcvtnu x21, d10 575083e807e2bb6b5bf2ab8fbc2e11bc 42b3366ecb91520d88ce4242917130fd 575083e807e2b…
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2440 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
2728 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>;
3272 defm FCVTNU : SIMDFPTwoScalar< 1, 0, 0b11010, "fcvtnu">;

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