Home
last modified time | relevance | path

Searched refs:fcvtpu (Results 1 – 23 of 23) sorted by relevance

/external/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s182 fcvtpu h12, h13
183 fcvtpu s12, s13
184 fcvtpu d21, d14
Darm64-fp-encoding.s380 fcvtpu w1, h2
381 fcvtpu w1, s2
382 fcvtpu w1, d2
383 fcvtpu x1, h2
384 fcvtpu x1, s2
385 fcvtpu x1, d2
387 ; FP16: fcvtpu w1, h2 ; encoding: [0x41,0x00,0xe9,0x1e]
389 ; NO-FP16-NEXT: fcvtpu w1, h2
390 ; CHECK: fcvtpu w1, s2 ; encoding: [0x41,0x00,0x29,0x1e]
391 ; CHECK: fcvtpu w1, d2 ; encoding: [0x41,0x00,0x69,0x1e]
[all …]
Dneon-simd-misc.s585 fcvtpu v4.4h, v0.4h
586 fcvtpu v6.8h, v8.8h
587 fcvtpu v6.4s, v8.4s
588 fcvtpu v6.2d, v8.2d
589 fcvtpu v4.2s, v0.2s
Dfullfp16-neon-neg.s244 fcvtpu h12, h13
342 fcvtpu v4.4h, v0.4h
344 fcvtpu v6.8h, v8.8h
Darm64-advsimd.s888 fcvtpu.2s v0, v0
889 fcvtpu.4s v0, v0
890 fcvtpu.2d v0, v0
891 fcvtpu s0, s0
892 fcvtpu d0, d0 define
894 ; CHECK: fcvtpu.2s v0, v0 ; encoding: [0x00,0xa8,0xa1,0x2e]
895 ; CHECK: fcvtpu.4s v0, v0 ; encoding: [0x00,0xa8,0xa1,0x6e]
896 ; CHECK: fcvtpu.2d v0, v0 ; encoding: [0x00,0xa8,0xe1,0x6e]
897 ; CHECK: fcvtpu s0, s0 ; encoding: [0x00,0xa8,0xa1,0x7e]
898 ; CHECK: fcvtpu d0, d0 ; encoding: [0x00,0xa8,0xe1,0x7e]
Dneon-diagnostics.s5906 fcvtpu v0.16b, v31.16b
5907 fcvtpu v2.8h, v4.8h
5908 fcvtpu v1.8b, v9.8b
5909 fcvtpu v13.4h, v21.4h
7282 fcvtpu s0, d0
7283 fcvtpu d0, s0 define
Dbasic-a64-instructions.s2079 fcvtpu w30, s23
2080 fcvtpu x29, s3
2133 fcvtpu w30, d23
2134 fcvtpu x29, d3
/external/llvm/test/CodeGen/AArch64/
Darm64-cvt.ll288 ;CHECK: fcvtpu w0, s0
290 %tmp3 = call i32 @llvm.aarch64.neon.fcvtpu.i32.f32(float %A)
296 ;CHECK: fcvtpu x0, s0
298 %tmp3 = call i64 @llvm.aarch64.neon.fcvtpu.i64.f32(float %A)
304 ;CHECK: fcvtpu w0, d0
306 %tmp3 = call i32 @llvm.aarch64.neon.fcvtpu.i32.f64(double %A)
312 ;CHECK: fcvtpu x0, d0
314 %tmp3 = call i64 @llvm.aarch64.neon.fcvtpu.i64.f64(double %A)
318 declare i32 @llvm.aarch64.neon.fcvtpu.i32.f32(float) nounwind readnone
319 declare i64 @llvm.aarch64.neon.fcvtpu.i64.f32(float) nounwind readnone
[all …]
Dround-conv.ll124 ; CHECK: fcvtpu w0, s0
134 ; CHECK: fcvtpu x0, s0
144 ; CHECK: fcvtpu w0, d0
154 ; CHECK: fcvtpu x0, d0
Darm64-vcvt.ll161 ;CHECK: fcvtpu.2s v0, v0
163 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtpu.v2i32.v2f32(<2 x float> %A)
170 ;CHECK: fcvtpu.4s v0, v0
172 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtpu.v4i32.v4f32(<4 x float> %A)
179 ;CHECK: fcvtpu.2d v0, v0
181 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtpu.v2i64.v2f64(<2 x double> %A)
185 declare <2 x i32> @llvm.aarch64.neon.fcvtpu.v2i32.v2f32(<2 x float>) nounwind readnone
186 declare <4 x i32> @llvm.aarch64.neon.fcvtpu.v4i32.v4f32(<4 x float>) nounwind readnone
187 declare <2 x i64> @llvm.aarch64.neon.fcvtpu.v2i64.v2f64(<2 x double>) nounwind readnone
/external/valgrind/docs/internals/
DMERGE_3_10_1.txt178 //2992 arm64: Implement "fcvtpu w, s". n-i-bz.
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt1703 # FP16: fcvtpu w30, h23
1704 # FP16: fcvtpu x29, h3
1757 # CHECK: fcvtpu w30, s23
1758 # CHECK: fcvtpu x29, s3
1811 # CHECK: fcvtpu w30, d23
1812 # CHECK: fcvtpu x29, d3
Dneon-instructions.txt2609 # CHECK: fcvtpu s12, s13
2610 # CHECK: fcvtpu d21, d14
Darm64-advsimd.txt477 # CHECK: fcvtpu.2s v0, v0
/external/vixl/src/vixl/a64/
Dmacro-assembler-a64.h1267 fcvtpu(rd, vn); in Fcvtpu()
2267 V(fcvtpu, Fcvtpu) \
Dassembler-a64.h2243 void fcvtpu(const Register& rd, const VRegister& vn);
2249 void fcvtpu(const VRegister& vd, const VRegister& vn);
Dassembler-a64.cc2862 V(fcvtpu, NEON_FCVTPU, FCVTPU) \
/external/vixl/test/
Dtest-simulator-a64.cc3990 DEFINE_TEST_NEON_2SAME_FP(fcvtpu, Conversions) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
4032 DEFINE_TEST_NEON_2SAME_FP_SCALAR(fcvtpu, Conversions)
Dtest-disasm-a64.cc2469 COMPARE(fcvtpu(x24, d25), "fcvtpu x24, d25"); in TEST()
2470 COMPARE(fcvtpu(w26, d27), "fcvtpu w26, d27"); in TEST()
2473 COMPARE(fcvtpu(x0, s1), "fcvtpu x0, s1"); in TEST()
2474 COMPARE(fcvtpu(w2, s3), "fcvtpu w2, s3"); in TEST()
/external/vixl/doc/
Dsupported-instructions.md2018 void fcvtpu(const Register& rd, const VRegister& vn)
2025 void fcvtpu(const VRegister& vd, const VRegister& vn)
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp26748 fcvtpu d21, d10 306ff161bcc49ffd542b8f375796551c f27be8de3d759706d3d2d4b3c3dc9f77 0000000000000…
26750 fcvtpu s21, s10 176150a2a7425cde2c48b536f8a9c25c 11f6ebf544d4152f5c99085c5bd397b1 0000000000000…
26752 fcvtpu v10.2d, v21.2d 0b27a1aac75bf20fe0481c8d9e68587b 9c2440b4e1afcd882324de3b585618aa 0000000…
26754 fcvtpu v10.4s, v21.4s 0cc1e3791d10628f732cc53c4ad3187a 9606e61a1305be1027725453ba642463 0000000…
26756 fcvtpu v10.2s, v21.2s 1b2e1610a860ac5ee2f3af42fbe90258 fd9bde28dbd7e9c768836da282fdb8db 0000000…
26758 fcvtpu w21, s10 386e3c6e684ccf7d309eda9fb2ab1515 d1e428de38244daee7592728af22d612 386e3c6e684cc…
26760 fcvtpu x21, s10 628252945ed4cbec5a2c47546e1851b3 13e1c33a2bedebc5a4f182e642d37e09 628252945ed4c…
26762 fcvtpu w21, d10 9a6a5b828af6a1aa639ef6603030b72f c291af3fb331c20b9d4e7fdb3b0fafc0 9a6a5b828af6a…
26764 fcvtpu x21, d10 df255437ebb551b848f4e6c4f7f4478b dff4edebd1f1d380d56d1d0898d66a36 df255437ebb55…
/external/valgrind/
DNEWS517 n-i-bz arm64: Implement "fcvtpu w, s".
814 335564 arm64: unhandled instruction: fcvtpu Xn, Sn
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2442 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
2740 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;
3274 defm FCVTPU : SIMDFPTwoScalar< 1, 1, 0b11010, "fcvtpu">;