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Searched refs:getConstantOperandVal (Results 1 – 17 of 17) sorted by relevance

/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp927 unsigned RotAmt = V.getConstantOperandVal(1); in getValueBits()
940 unsigned ShiftAmt = V.getConstantOperandVal(1); in getValueBits()
956 unsigned ShiftAmt = V.getConstantOperandVal(1); in getValueBits()
972 uint64_t Mask = V.getConstantOperandVal(1); in getValueBits()
3010 int Elt = N->getConstantOperandVal(0); in Select()
3011 int EltSize = N->getConstantOperandVal(1); in Select()
3116 uint64_t PM = O.getConstantOperandVal(2); in combineToCMPB()
3117 uint64_t PAlt = O.getConstantOperandVal(3); in combineToCMPB()
3130 O.getConstantOperandVal(1) != 0) { in combineToCMPB()
3144 if (Op0.getConstantOperandVal(1) != Bits-8) in combineToCMPB()
[all …]
/external/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp616 if (N->getConstantOperandVal(1)) in PreprocessISelDAG()
926 int ScaleLog = 8 - Shift.getConstantOperandVal(1); in foldMaskAndShiftToExtract()
975 unsigned ShiftAmt = Shift.getConstantOperandVal(1); in foldMaskedShiftToScaledMask()
1035 unsigned ShiftAmt = Shift.getConstantOperandVal(1); in foldMaskAndShiftToScale()
1225 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1); in matchAddressRecursively()
1376 uint64_t Mask = N.getConstantOperandVal(1); in matchAddressRecursively()
DX86ISelLowering.cpp5329 Offset = Ptr.getConstantOperandVal(1); in LowerAsSplatVectorLoad()
13888 unsigned ShAmt = Op->getConstantOperandVal(1); in EmitTest()
14718 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); in LowerSETCC()
15601 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); in LowerBRCOND()
15619 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); in LowerBRCOND()
15632 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); in LowerBRCOND()
15896 unsigned Align = Op.getConstantOperandVal(3); in LowerVAARG()
24555 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B && in checkBoolTestSetCCCombine()
24560 CC = X86::CondCode(SetCC.getConstantOperandVal(0)); in checkBoolTestSetCCCombine()
24598 CC = X86::CondCode(SetCC.getConstantOperandVal(2)); in checkBoolTestSetCCCombine()
[all …]
/external/llvm/include/llvm/CodeGen/
DSelectionDAGNodes.h162 inline uint64_t getConstantOperandVal(unsigned i) const;
629 uint64_t getConstantOperandVal(unsigned Num) const;
944 inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
945 return Node->getConstantOperandVal(i);
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypesGeneric.cpp306 const unsigned Align = N->getConstantOperandVal(3); in ExpandRes_VAARG()
DInstrEmitter.cpp761 CC = Node->getConstantOperandVal(PatchPointOpers::CCPos); in EmitMachineNode()
DSelectionDAG.cpp1845 unsigned Align = Node->getConstantOperandVal(3); in expandVAArg()
3145 Operand.getConstantOperandVal(1) == 0 && in getNode()
6924 uint64_t SDNode::getConstantOperandVal(unsigned Num) const { in getConstantOperandVal() function in SDNode
7089 FrameOffset = Ptr.getConstantOperandVal(1); in InferPtrAlignment()
DLegalizeFloatTypes.cpp680 N->getConstantOperandVal(3)); in SoftenFloatRes_VAARG()
DDAGCombiner.cpp9036 const bool NIsTrunc = N->getConstantOperandVal(1) == 1; in visitFP_ROUND()
9037 const bool N0IsTrunc = N0.getNode()->getConstantOperandVal(1) == 1; in visitFP_ROUND()
9110 && N0.getNode()->getConstantOperandVal(1) == 1) { in visitFP_EXTEND()
13008 unsigned Idx = N->getConstantOperandVal(1); in visitEXTRACT_SUBVECTOR()
DLegalizeIntegerTypes.cpp824 N->getConstantOperandVal(3)); in PromoteIntRes_VAARG()
DLegalizeDAG.cpp4293 Node->getConstantOperandVal(3)); in PromoteNode()
/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp1038 assert(SetCC->getConstantOperandVal(1) == 1); in LowerBRCOND()
2205 unsigned OldDmask = Node->getConstantOperandVal(0); in adjustWritemask()
2221 Lane = SubIdx2Lane(I->getConstantOperandVal(1)); in adjustWritemask()
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp1414 return DAG.getConstant(Op->getConstantOperandVal(ImmOp), SDLoc(Op), in lowerMSASplatImm()
1593 Op->getConstantOperandVal(3)); in lowerINTRINSIC_WO_CHAIN()
1606 Op->getConstantOperandVal(3)); in lowerINTRINSIC_WO_CHAIN()
DMipsISelLowering.cpp1859 unsigned Align = Node->getConstantOperandVal(3); in lowerVAARG()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp3639 isPowerOf2_64(LHS.getConstantOperandVal(1))) { in LowerBR_CC()
3641 uint64_t Mask = LHS.getConstantOperandVal(1); in LowerBR_CC()
3655 isPowerOf2_64(LHS.getConstantOperandVal(1))) { in LowerBR_CC()
3657 uint64_t Mask = LHS.getConstantOperandVal(1); in LowerBR_CC()
4287 unsigned Align = Op.getConstantOperandVal(3); in LowerVAARG()
7305 uint64_t TruncMask = N->getConstantOperandVal(1); in isDesirableToCommuteWithShift()
7704 ShiftAmount = N->getConstantOperandVal(1); in findEXTRHalf()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp2580 uint64_t depth = Op.getConstantOperandVal(0); in LowerFRAMEADDR()
2598 uint64_t depth = Op.getConstantOperandVal(0); in LowerRETURNADDR()
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1116 MemN->getConstantOperandVal(MemN->getNumOperands() - 1) == 1)) { in SelectAddrMode6()